博通BCM5396交换芯片技术手册
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更新于2024-07-09
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"博通BCM5396交换芯片是一款单片16端口SerDes千兆交换芯片，专为桌面交换解决方案或WebSmart应用提供最低成本的千兆以太网功能。这款高度集成的解决方案将高速交换系统所需的所有功能，如包缓冲器、媒体访问控制器（MACs）、地址管理和非阻塞交换控制器整合到一个单一的0.13微米CMOS设备中。它符合IEEE 802.3系列标准，包括MAC控制PAUSE帧和自动协商子部分，确保与所有行业标准的以太网、快速以太网和千兆以太网设备兼容。BCM5396还集成了1.25G SerDes，减少了电路板空间需求。每个端口支持SGMII接口，用于连接外部千兆PHY或光纤模块。"
博通BCM5396交换芯片详细手册详细介绍了这款芯片的特性、功能和应用场景。其主要特点包括：
1. **16端口集成**: BCM5396芯片提供了16个千兆以太网端口，每个端口都具备1.25G SerDes接口，可以连接到外部的千兆物理层（PHY）设备或光纤模块，降低了硬件设计的复杂性。
2. **高度集成**: 这款芯片将交换机系统的关键组件，如包缓冲、MACs、地址管理以及非阻塞交换控制器集成在一起，这使得它能够在单一芯片上实现完整的千兆以太网交换功能，减少了外部组件的需求，从而降低了整体成本。
3. **符合标准**: BCM5396遵循了IEEE 802.3系列标准，包括802.3ab（千兆以太网 over copper）和802.3x（流量控制），确保与广泛使用的以太网设备兼容，并支持MAC控制PAUSE帧，允许动态调整网络带宽。
4. **低功耗和小型化**: 采用0.13微米CMOS工艺制造，该芯片实现了低功耗设计，同时集成的SerDes减少了电路板的空间占用，适合于紧凑型网络设备设计。
5. **WebSmart应用**: BCM5396特别适用于桌面交换解决方案和WebSmart应用，WebSmart是一种具有基本智能功能的交换设备，能够进行简单的网络管理和故障排查。
在开发基于博通BCM5396的以太网交换产品时，工程师需要理解这些特性并充分利用它们。例如，为了优化电路板布局，他们需要了解如何有效地利用集成的SerDes接口，并确保与兼容的PHY设备进行通信。此外，理解和实施802.3标准中的功能，如PAUSE帧和自动协商，对于构建一个稳定且兼容性强的网络解决方案至关重要。通过深入研究BCM5396的手册，开发者可以获取关于配置、性能优化以及故障排除等详细信息，以创建高效且可靠的网络交换设备。
List of Figures BCM5396 Data Sheet
BROADCOM Single-Chip 16-Port SerDes Gigabit Switch
October 4, 2013 • 5396-DS114-R Page 16
®
BROADCOM CONFIDENTIAL
List of Figures
Figure 1: Functional Block Diagram....................................................................................................................2
Figure 2: Priority Packet Mapping Flow ...........................................................................................................27
Figure 3: VLAN Table Organization...................................................................................................................31
Figure 4: Bucket Flow .......................................................................................................................................34
Figure 5: Mirror Filter Flow ..............................................................................................................................36
Figure 6: Address Table Organization...............................................................................................................39
Figure 7: TXQ and Buffer Tag Structure............................................................................................................54
Figure 8: RvMII Port Connections.....................................................................................................................57
Figure 9: Normal SPI Command Byte ...............................................................................................................61
Figure 10: Fast SPI Command Byte...................................................................................................................61
Figure 11: SPI Serial Interface Write Operation ...............................................................................................62
Figure 12: SPI Serial Interface Read Operation ................................................................................................62
Figure 13: Normal SPI Mode Read Flow Chart .................................................................................................63
Figure 14: Normal SPI Mode Write Flow Chart ................................................................................................65
Figure 15: Timing Example ...............................................................................................................................66
Figure 16: Serial EEPROM Connection .............................................................................................................67
Figure 17: MDC/MDIO Interface ......................................................................................................................68
Figure 18: Read Access to Switch via Pseudo-PHY (PHY ADD = 1_1110) MDC[0]/MDIO[0] Path.....................69
Figure 19: Write Access to Switch via Pseudo-PHY (PHY ADD = 1_1110) MDC[0]/MDIO[0] Path....................70
Figure 20: Pseudo-PHY MII Register Map.........................................................................................................71
Figure 21: Pins Top View ..................................................................................................................................88
Figure 22: Reset and Clock Timing .................................................................................................................182
Figure 23: RvMII Mode Output Timings .........................................................................................................183
Figure 24: RvMII Mode Input Timings ............................................................................................................183
Figure 25: RGMII Output Timing (Normal Mode)...........................................................................................184
Figure 26: RGMII Output Timing (Delayed Mode)..........................................................................................185
Figure 27: RGMII Input Timing (Normal Mode)..............................................................................................186
Figure 28: RGMII Input Timing (Delayed Mode).............................................................................................187
Figure 29: GMII Output Timing.......................................................................................................................188
Figure 30: GMII Input Timing..........................................................................................................................188
Figure 31: Serial Interface Output Timing ......................................................................................................189
Figure 32: Serial Interface Input Timing .........................................................................................................190
Figure 33: MDC/MDIO Timing ........................................................................................................................190
Figure 34: Serial LED Interface Timing............................................................................................................191
Figure 35: SPI Timings, SS
Asserted During SCK High .....................................................................................192
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