没有合适的资源?快使用搜索试试~ 我知道了~
首页CC2538用户指南:ARM Cortex-M3为基础的IEEE 802.15.4 RF芯片解决方案
CC2538用户指南:ARM Cortex-M3为基础的IEEE 802.15.4 RF芯片解决方案
需积分: 19 9 下载量 75 浏览量
更新于2024-07-23
收藏 4.64MB PDF 举报
"CC2538用户手册是针对CC2538微处理器的一份详细软件库文档,该处理器基于ARM Cortex-M3内核,符合IEEE 802.15.4标准,适用于2.4GHz的ZigBee和ZigBee IP应用。这份用户指南涵盖了CC2538系列产品的版本C,由德州仪器(Texas Instruments)发布,文献编号为SWRU319C,首次出版于2012年4月,并在2013年5月进行了修订。"
本文档主要知识点:
1. **CC2538微处理器**: CC2538是一款集成射频(RF)系统的单芯片解决方案,专为2.4 GHz频段的IEEE 802.15.4标准设计,支持ZigBee和ZigBee IP网络。它采用ARM Cortex-M3架构,提供高性能和低功耗的特性。
2. **基础固件组件**: 基础固件包含了多个软件库,这些库可能包括驱动程序、协议栈、中间件和应用程序示例,以帮助开发者快速构建无线物联网应用。
3. **ZigBee技术**: ZigBee是一种基于IEEE 802.15.4标准的无线通信协议,用于设备间的短距离、低功耗数据传输,常用于智能家居、工业自动化和物联网等领域。
4. **ZigBee IP**: ZigBee IP是ZigBee网络的一个扩展,允许设备通过IP地址进行通信,使得ZigBee设备可以接入互联网并与其他IP网络设备交互。
5. **ARM Cortex-M3**: ARM Cortex-M3是一款面向微控制器的RISC处理器核心,具有高效能和低功耗的特点,适合于嵌入式系统,尤其是物联网设备。
6. **MPU (Microprocessor Unit)**: MPU在本手册中指CC2538中的微处理器单元,负责处理系统的主要运算任务。
7. **出口管制**: 用户指南中提到了出口管制注意事项,提醒接收方在出口或转口产品和技术时必须遵守美国、欧盟和其他国家的出口管理法规,特别是涉及技术数据和双重用途商品的法规。
8. **用户指南内容**: 用户指南应包含CC2538的硬件描述、编程接口、API文档、配置选项、应用实例以及故障排查等内容,帮助开发者理解和使用CC2538芯片进行开发。
9. **版本控制**: 版本C表示该文档的当前版本,可能包括了之前版本的改进和修复,开发者需要根据具体项目需求选择合适版本的文档。
10. **合规性**: 文档提及了对产品或技术状态和最终用途的了解,强调了遵守相关国家的出口控制法规,确保开发和应用过程的合法性。
CC2538用户手册提供了全面的开发和应用指南,涵盖了从硬件到软件的各个层面,旨在帮助开发者充分利用CC2538在ZigBee和物联网领域的潜力。同时,手册还强调了遵守出口管制规定的重要性,以确保全球范围内的合法使用。
Public Version
www.ti.com
23.14 Command Strobe/CSMA-CA Processor .............................................................................. 687
23.14.1 Instruction Memory ........................................................................................... 687
23.14.2 Data Registers ................................................................................................ 687
23.14.3 Program Execution ........................................................................................... 688
23.14.4 Interrupt Requests ............................................................................................ 688
23.14.5 Random Number Instruction ................................................................................ 688
23.14.6 Running CSP Programs ..................................................................................... 688
23.14.7 CSP Registers ................................................................................................ 689
23.14.8 Instruction Set Summary .................................................................................... 690
23.14.9 Instruction Set Definition ..................................................................................... 691
23.14.9.1 DECZ ...................................................................................................... 691
23.14.9.2 DECY ..................................................................................................... 692
23.14.9.3 DECX ..................................................................................................... 692
23.14.9.4 INCZ ....................................................................................................... 692
23.14.9.5 INCY ...................................................................................................... 692
23.14.9.6 INCX ...................................................................................................... 692
23.14.9.7 INCMAXY ................................................................................................. 693
23.14.9.8 RANDXY .................................................................................................. 693
23.14.9.9 INT ......................................................................................................... 693
23.14.9.10 WAITX ................................................................................................... 693
23.14.9.11 SETCMP1 ............................................................................................... 694
23.14.9.12 WAIT W ................................................................................................. 694
23.14.9.13 WEVENT1 .............................................................................................. 694
23.14.9.14 WEVENT2 .............................................................................................. 695
23.14.9.15 LABEL ................................................................................................... 695
23.14.9.16 RPT C ................................................................................................... 695
23.14.9.17 SKIP S, C ............................................................................................... 696
23.14.9.18 STOP .................................................................................................... 696
23.14.9.19 SNOP .................................................................................................... 697
23.14.9.20 SRXON .................................................................................................. 697
23.14.9.21 STXON .................................................................................................. 697
23.14.9.22 STXONCCA ............................................................................................ 697
23.14.9.23 SSAMPLECCA ......................................................................................... 698
23.14.9.24 SRFOFF ................................................................................................. 698
23.14.9.25 SFLUSHRX ............................................................................................. 698
23.14.9.26 SFLUSHTX ............................................................................................. 698
23.14.9.27 SACK .................................................................................................... 698
23.14.9.28 SACKPEND ............................................................................................. 699
23.14.9.29 SNACK .................................................................................................. 699
23.14.9.30 SRXMASKBITSET ..................................................................................... 699
23.14.9.31 SRXMASKBITCLR ..................................................................................... 699
23.14.9.32 ISSTOP .................................................................................................. 700
23.14.9.33 ISSTART ................................................................................................ 700
23.14.9.34 ISRXON ................................................................................................. 700
23.14.9.35 ISRXMASKBITSET .................................................................................... 700
23.14.9.36 ISRXMASKBITCLR .................................................................................... 701
23.14.9.37 ISTXON ................................................................................................. 701
23.14.9.38 ISTXONCCA ............................................................................................ 701
23.14.9.39 ISSAMPLECCA ........................................................................................ 701
23.14.9.40 ISRFOFF ................................................................................................ 702
23.14.9.41 ISFLUSHRX ............................................................................................ 702
23.14.9.42 ISFLUSHTX ............................................................................................. 702
23.14.9.43 ISACK ................................................................................................... 702
16
Contents SWRU319C–April 2012–Revised May 2013
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Public Version
www.ti.com
23.14.9.44 ISACKPEND ............................................................................................ 702
23.14.9.45 ISNACK ................................................................................................. 703
23.14.9.46 ISCLEAR ................................................................................................ 703
23.15 Register Settings Update ............................................................................................... 703
23.16 Radio Registers .......................................................................................................... 704
23.16.1 RFCORE_FFSM Registers ................................................................................. 704
23.16.1.1 RFCORE_FFSM Registers Mapping Summary ..................................................... 704
23.16.1.2 RFCORE_FFSM Register Descriptions .............................................................. 705
23.16.2 RFCORE_XREG Registers ................................................................................. 712
23.16.2.1 RFCORE_XREG Registers Mapping Summary ..................................................... 712
23.16.2.2 RFCORE_XREG Register Descriptions .............................................................. 715
23.16.3 RFCORE_SFR Registers ................................................................................... 748
23.16.3.1 RFCORE_SFR Registers Mapping Summary ....................................................... 749
23.16.3.2 RFCORE_SFR Register Descriptions ................................................................ 749
23.16.4 CCTEST Registers ........................................................................................... 752
23.16.4.1 CCTEST Registers Mapping Summary .............................................................. 752
23.16.4.2 CCTEST Register Descriptions ........................................................................ 752
23.16.5 ANA_REGS Registers ....................................................................................... 757
23.16.5.1 ANA_REGS Registers Mapping Summary ........................................................... 757
23.16.5.2 ANA_REGS Register Descriptions .................................................................... 757
24 Voltage Regulator ............................................................................................................ 759
A Available Software ........................................................................................................... 760
A.1 SmartRF™ Studio Software for Evaluation (www.ti.com/smartrfstudio) .......................................... 761
A.2 TIMAC Software (www.ti.com/timac) .................................................................................. 761
A.3 Z-Stack™ Software (www.ti.com/z-stack) ............................................................................ 761
B Abbreviations .................................................................................................................. 763
C Additional Information ...................................................................................................... 766
C.1 Texas Instruments Low-Power RF Web Site ......................................................................... 767
C.2 Low-Power RF Online Community ..................................................................................... 767
C.3 Texas Instruments Low-Power RF Developer Network ............................................................. 767
C.4 Low-Power RF eNewsletter ............................................................................................. 767
D References ...................................................................................................................... 768
E Revision History .............................................................................................................. 769
E.1 Revision History – External ............................................................................................. 769
17
SWRU319C–April 2012–Revised May 2013 Contents
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Public Version
www.ti.com
List of Figures
1-1. CC2538 Block Diagram................................................................................................... 34
2-1. CPU Block Diagram....................................................................................................... 47
2-2. TPIU Block Diagram ...................................................................................................... 48
2-3. Cortex-M3 Register Set................................................................................................... 50
3-1. SRD Use Example ........................................................................................................ 71
4-1. Bit-Band Mapping ........................................................................................................ 161
4-2. Data Storage.............................................................................................................. 162
5-1. Vector Table .............................................................................................................. 171
5-2. Exception Stack Frame ................................................................................................. 173
6-1. Test/Debug System Top Level Diagram .............................................................................. 178
7-1. Flow Diagram for Operational Modes ................................................................................. 186
7-2. Simple Flow Diagram for Power Management....................................................................... 188
7-3. Timing Example for Transition from 32 MHz to PM's ............................................................... 190
7-4. Simplified Figure of Current Consumption in PM1 .................................................................. 192
7-5. Simplified Figure of Current Consumption in PM2 and PM3....................................................... 192
7-6. Block Diagram Oscillators and Clocks ................................................................................ 193
8-1. Flash Write Using DMA ................................................................................................. 218
9-1. Digital I/O Pads (The Diagram Shows One of 32 Possible I/O Pins) ............................................. 233
9-2. GPIODATA Write Example ............................................................................................. 234
9-3. GPIODATA Read Example ............................................................................................. 234
9-4. PAD Configuration Override Registers................................................................................ 237
10-1. μDMA Block Diagram ................................................................................................... 287
10-2. Example of Ping-Pong μDMA Transaction ........................................................................... 293
10-3. Memory Scatter-Gather, Setup and Configuration .................................................................. 295
10-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................................... 296
10-5. Peripheral Scatter-Gather, Setup and Configuration................................................................ 298
10-6. Peripheral Scatter-Gather, μDMA Copy Sequence ................................................................. 299
11-1. GPTM Module Block Diagram.......................................................................................... 319
11-2. Input Edge-Count Mode Example, Counting Down ................................................................. 323
11-3. Input Edge-Time Mode Example....................................................................................... 324
11-4. 16-bit PWM Mode Example ............................................................................................ 326
11-5. CCP Output, GPTIMER_TnMATCHR > GPTIMER_TnILR ........................................................ 326
11-6. CCP Output, GPTIMER_TnMATCHR = GPTIMER_TnILR ........................................................ 327
11-7. CCP Output, GPTIMER_TnILR > GPTIMER_TnMATCHR ........................................................ 327
11-8. Timer Daisy-Chain ....................................................................................................... 328
13-1. Sleep timer Capture ..................................................................................................... 364
15-1. ADC Block Diagram ..................................................................................................... 374
16-1. Basic Structure of the RNG............................................................................................. 382
17-1. Analog Comparator ...................................................................................................... 386
18-1. UART Module Block Diagram .......................................................................................... 390
18-2. UART Character Frame................................................................................................. 391
18-3. LIN Message.............................................................................................................. 393
18-4. LIN Synchronization Field............................................................................................... 394
19-1. SSI Module Block Diagram ............................................................................................. 416
19-2. TI Synchronous Serial Frame Format (Single Transfer)............................................................ 419
19-3. TI Synchronous Serial Frame Format (Continuous Transfer)...................................................... 419
19-4. Freescale SPI Format (Single Transfer) With SPO = 0 and SPH = 0 ............................................ 420
18
List of Figures SWRU319C–April 2012–Revised May 2013
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Public Version
www.ti.com
19-5. Freescale SPI Format (Continuous Transfer) With SPO = 0 and SPH = 0 ...................................... 420
19-6. Freescale SPI Frame Format With SPO = 0 and SPH = 1......................................................... 421
19-7. Freescale SPI Frame Format (Single Transfer) With SPO = 1 and SPH = 0.................................... 421
19-8. Freescale SPI Frame Format (Continuous Transfer) With SPO = 1 and SPH = 0.............................. 422
19-9. Freescale SPI Frame Format With SPO = 1 and SPH = 1......................................................... 422
19-10. MICROWIRE Frame Format (Single Frame)......................................................................... 423
19-11. MICROWIRE Frame Format (Continuous Transfer) ................................................................ 424
19-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ..................................... 424
20-1. I
2
C Block Diagram........................................................................................................ 435
20-2. I
2
C Bus Configuration.................................................................................................... 436
20-3. Start and Stop Conditions............................................................................................... 436
20-4. Complete Data Transfer With a 7-Bit Address ....................................................................... 437
20-5. R/S Bit in First Byte...................................................................................................... 437
20-6. Data Validity During Bit Transfer on the I
2
C Bus..................................................................... 437
20-7. Master Single TRANSMIT .............................................................................................. 440
20-8. Master Single RECEIVE ................................................................................................ 441
20-9. Master TRANSMIT With Repeated Start Condition ................................................................. 442
20-10. Master RECEIVE With Repeated Start Condition ................................................................... 443
20-11. Master RECEIVE With Repeated Start After TRANSMIT With Repeated Start Condition..................... 444
20-12. Master TRANSMIT With Repeated Start After RECEIVE With Repeated Start Condition..................... 445
20-13. Slave Command Sequence ............................................................................................ 446
21-1. USB Controller Block Diagram ......................................................................................... 458
21-2. USB Interrupt Service Routine ......................................................................................... 460
21-3. Endpoint 0 States ........................................................................................................ 465
21-4. Endpoint 0 Service Routine............................................................................................. 466
21-5. SETUP Phase of Control Transfer..................................................................................... 468
21-6. SETUP Phase Control Transactions .................................................................................. 469
21-7. IN Data Phase for Control Transfer ................................................................................... 470
21-8. IN Phase Control Transactions......................................................................................... 471
21-9. Control Transactions Following Status Stage (TX Mode) .......................................................... 472
21-10. OUT Data Phase for Control Transfer ................................................................................ 473
21-11. OUT Phase Control Transactions...................................................................................... 474
21-12. Control Transactions Following Status Stage (RX Mode) .......................................................... 475
21-13. IN/OUT FIFOs ............................................................................................................ 476
21-14. Bulk and Interrupt IN Transactions .................................................................................... 479
21-15. Isochronous IN Transactions ........................................................................................... 481
21-16. Bulk and Interrupt OUT Transactions ................................................................................. 483
21-17. Isochronous OUT Transactions ........................................................................................ 485
22-1. Operation Sequences and Main Interrupt ............................................................................ 525
22-2. DMA Controller and Its Integration .................................................................................... 534
22-3. Symmetric Crypto Processing Steps .................................................................................. 568
22-4. Implementation of Secure HMAC Operation ......................................................................... 575
22-5. AIC: Functional Logic of one Interrupt Source ....................................................................... 591
23-1. Modulation ................................................................................................................ 664
23-2. I and Q Phases When Transmitting a Zero-Symbol Chip Sequence, t
C
= 0.5 μs ............................... 665
23-3. Schematic View of the IEEE 802.15.4 Frame Format .............................................................. 665
23-4. Format of the Frame Control Field (FCF)............................................................................. 666
23-5. Frame Data Written to the TX FIFO ................................................................................... 667
23-6. TX Flow.................................................................................................................... 669
19
SWRU319C–April 2012–Revised May 2013 List of Figures
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Public Version
www.ti.com
23-7. Transmitted Synchronization Header.................................................................................. 670
23-8. FCS Hardware Implementation ........................................................................................ 671
23-9. SFD Signal Timing....................................................................................................... 673
23-10. Filtering Scenarios (Exceptions Generated During Reception) .................................................... 675
23-11. Matching Algorithm for Short and Extended Addresses ............................................................ 677
23-12. Interrupts Generated by Source Address Matching ................................................................. 678
23-13. Data in RX FIFO for Different Settings................................................................................ 679
23-14. Acknowledge Frame Format ........................................................................................... 679
23-15. Acknowledgement Timing............................................................................................... 680
23-16. Command Strobe Timing ............................................................................................... 680
23-17. Behavior of FIFO and FIFOP Signals ................................................................................. 682
23-18. Main FSM ................................................................................................................. 684
23-19. FFT of the Random Bytes .............................................................................................. 685
23-20. Histogram of 20 Million Bytes Generated With the RANDOM Instruction ........................................ 686
23-21. Running a CSP Program................................................................................................ 689
20
List of Figures SWRU319C–April 2012–Revised May 2013
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
剩余769页未读,继续阅读
2014-10-03 上传
2018-08-24 上传
点击了解资源详情
点击了解资源详情
2017-12-06 上传
2018-07-20 上传
2015-11-15 上传
jhzhu123
- 粉丝: 0
- 资源: 1
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
最新资源
- 深入浅出:自定义 Grunt 任务的实践指南
- 网络物理突变工具的多点路径规划实现与分析
- multifeed: 实现多作者间的超核心共享与同步技术
- C++商品交易系统实习项目详细要求
- macOS系统Python模块whl包安装教程
- 掌握fullstackJS:构建React框架与快速开发应用
- React-Purify: 实现React组件纯净方法的工具介绍
- deck.js:构建现代HTML演示的JavaScript库
- nunn:现代C++17实现的机器学习库开源项目
- Python安装包 Acquisition-4.12-cp35-cp35m-win_amd64.whl.zip 使用说明
- Amaranthus-tuberculatus基因组分析脚本集
- Ubuntu 12.04下Realtek RTL8821AE驱动的向后移植指南
- 掌握Jest环境下的最新jsdom功能
- CAGI Toolkit:开源Asterisk PBX的AGI应用开发
- MyDropDemo: 体验QGraphicsView的拖放功能
- 远程FPGA平台上的Quartus II17.1 LCD色块闪烁现象解析
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功