Section number Title Page
15.4.16
PAMU Operation Error Status register 2 (PAMUx_POES2)...................................................................... 480
15.4.17
PAMU Operation Error Address High register (PAMUx_POEAH)........................................................... 480
15.4.18
PAMU Operation Error Address Low register (PAMUx_POEAL)............................................................ 480
15.4.19
Access Violation Status register 1 (PAMUx_AVS1).................................................................................. 481
15.4.20
Access Violation Status register 2 (PAMUx_AVS2).................................................................................. 483
15.4.21
Access Violation Address High register (PAMUx_AVAH)........................................................................484
15.4.22
Access Violation Address Low register (PAMUx_AVAL).........................................................................484
15.4.23
ECC Error Control Register (PAMUx_EECTL)......................................................................................... 484
15.4.24
ECC Error Interrupt Enable Register (PAMUx_EEINTEN)....................................................................... 485
15.4.25
ECC Error Detect Register (PAMUx_EEDET)...........................................................................................486
15.4.26
ECC Error Attributes Register (PAMUx_EEATTR)...................................................................................487
15.4.27
ECC Error Address High (PAMUx_EEAHI).............................................................................................. 488
15.4.28
ECC Error Address Low (PAMUx_EEALO)..............................................................................................488
15.4.29
ECC Error Data High (PAMUx_EEDHI)....................................................................................................489
15.4.30
ECC Error Data Low (PAMUx_EEDLO)................................................................................................... 489
15.4.31
Unauthorized device access detection register (PAMUx_UDAD).............................................................. 490
15.4.32
PAMU Revision register 1 (PAMUx_PR1).................................................................................................490
15.4.33
PAMU Revision register 2 (PAMUx_PR2).................................................................................................491
15.4.34
PAMU Capabilities register 2 (PAMUx_PC2)............................................................................................ 491
15.4.35
PAMU Capabilities register 3 (PAMUx_PC3)............................................................................................ 493
15.4.36
PAMU Capabilities register 4 (PAMUx_PC4)............................................................................................ 495
15.4.37
PAMU Control register (PAMUx_PC)........................................................................................................496
15.4.38
PAMU Interrupt Control and Status register (PAMUx_PICS)....................................................................497
15.5 PAMU Functional Description..................................................................................................................................... 498
15.5.1 System Set-Up for PAMU Operation.......................................................................................................... 498
15.5.2 Steps in Processing of DSA Operations by PAMU..................................................................................... 499
15.5.3 Detailed Description of PAMU Actions...................................................................................................... 501
15.5.3.1 PAMU Gate Closed and PAMU Enable Check.......................................................................501
15.5.3.2 PPAACT Request Range Check..............................................................................................502
B4860 QorIQ Qonverge Multicore Baseband Processor Reference Manual, Rev. J, 07/2014
18
Preliminary
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