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1k32uww5g31if-eypl957l * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
1k32uww5g31if-eypl957l * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
1k32uww5g31if-eypl957l * Wintech Microelectronics Co. Ltd. - China * UNDER NDA# 12102018
MARVELL CONFIDENTIAL
JDK Use Only
88W8686
Datasheet
Doc. No. MV-S103343-00 Rev. D
CONFIDENTIAL
Copyright © 2007 Marvell
Page 18 Document Classification: Proprietary February 20, 2007, 2.00
Table 36: 24 MHz Reference Frequency ......................................................................................................... 88
Table 37: 26 MHz Reference Frequency ......................................................................................................... 90
Table 38: 38.4 MHz Reference Frequency ...................................................................................................... 92
Table 39: 40 MHz Reference Frequency ......................................................................................................... 94
Table 40: CCMP/AES Registers ...................................................................................................................... 97
Table 41: TKIP/WEP Registers........................................................................................................................ 98
Table 42: BCA Registers ............................................................................................................................... 102
Table 43: Single Antenna Default Arbitration Table....................................................................................... 107
Table 44: Dual Antenna Default Arbitration Table ......................................................................................... 107
Table 45: Arbiter Decision Table (BT_FREQ_OOB Bit = 1, Always InBand)................................................. 110
Table 46: Arbiter Decision Table, Bluetooth 1.2 Device (BT_FREQ_OOB Bit = 0, Always OutofBand)........ 111
Table 47: Arbiter Decision Table, Bluetooth 1.2/1.1 Device .......................................................................... 112
Table 48: Arbitration Table Variables............................................................................................................. 112
Table 49: SM Input Ports and States ............................................................................................................. 113
Table 50: SM Port List ................................................................................................................................... 114
Section 4. Host Interfaces .............................................................................................. 115
Table 51: G-SPI Interface Description ........................................................................................................... 116
Table 52: G-SPI Interface Registers Memory Space..................................................................................... 121
Table 53: Internal SQU Memory Space ......................................................................................................... 122
Table 54: SDIO Interface Signal Description ................................................................................................. 125
Table 55: SDIO Electrical Function Definition................................................................................................ 127
Table 56: SDIO Mode, SDIO Commands ...................................................................................................... 128
Table 57: SPI Mode, SDIO Commands ......................................................................................................... 128
Table 58: SDIO Registers .............................................................................................................................. 129
Section 5. Peripheral Bus Interface............................................................................... 131
Table 59: TWSI Registers.............................................................................................................................. 133
Table 60: 1-Wire Interface Registers ............................................................................................................. 136
Table 61: SPI EEPROM Interface Description............................................................................................... 137
Table 62: Write and Read Sequence Registers............................................................................................. 138
Table 63: UART Clock Divisor ....................................................................................................................... 141
Table 64: UART Pin Definitions ..................................................................................................................... 142
Table 65: UART Boot Requirements ............................................................................................................. 142
Table 66: GPIO Functions ............................................................................................................................. 144
Section 6. Electrical Specifications............................................................................... 145
Table 67: Absolute Maximum Ratings ........................................................................................................... 145
Table 68: Operating Conditions ..................................................................................................................... 146
Table 69: Internal Operating Frequencies ..................................................................................................... 146
Table 70: DC Electricals—3V Pads (VDD30) ................................................................................................ 147
Table 71: DC Electricals—1.8V/3.3V (VIO_X1/VIO_X2)................................................................................ 147
Table 72: Thermal Conditions—68-Pin (8x8x1 mm)...................................................................................... 149
Table 73: Flip Chip Thermal Conditions—280 μm Pitch ................................................................................ 150