Marvell 88W8686：集成802.11 a/g/b基带RF低功耗SoC芯片详细规格

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Marvell 88W8686是一款集成的多标准无线局域网（MAC）、基带和射频低功耗系统-on-a-chip (SoC)，专为支持IEEE 802.11a/g/b无线标准而设计。该芯片手册，文档编号MV-S103343-00, Rev.D，发布于2007年2月20日，属于Marvell公司的专有资料，受非披露协议（NDA）#12102018保护，仅限内部使用。该芯片的特点包括： 1. **功能集成**：88W8686集成了MAC层处理网络通信，基带功能负责数据调制解调，以及RF（射频）模块，实现了从无线信号接收、处理到传输的一体化解决方案，简化了系统设计并提高了效率。 2. **标准支持**：它支持多个Wi-Fi标准，即IEEE 802.11a/g/b，这意味着设备能提供高速的数据传输速率，适用于不同的应用场景，如家庭、办公室或公共场所的无线网络。 3. **低功耗设计**：作为低功耗SoC，88W8686特别注重能源管理，这对于移动设备和电池供电设备尤为重要，可以延长设备的电池续航时间。 4. **文档规范**：手册中包含了一系列的文档分类，如注释、注意事项、警告等，用于指导用户正确理解和使用芯片，同时也强调了可能存在的风险和安全措施。 5. **版本与状态**：文档状态标明为2.00，表示这是当前的官方发行版本，可能包含了后续更新和改进的内容。 6. **版权归属**：文档由Wintech Microelectronics Co., Ltd.在中国发行，表明这是一家与Marvell合作的公司，可能负责芯片在中国市场的销售和技术支持。 Marvell 88W8686 Datasheet提供了关于这款高性能且低功耗的Wi-Fi SoC的关键技术信息，对于开发人员、系统集成商和硬件工程师来说，是设计和优化基于此芯片无线产品的宝贵参考资料。在实际应用中，用户需要遵循NDA规定，确保信息的保密性和合规性。

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MARVELL CONFIDENTIAL, UNDER NDA# 12102018

1k32uww5g31if-eypl957l * Wintech Microelectronics Co. Ltd. - China

MARVELL CONFIDENTIAL, UNDER NDA# 12102018

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MARVELL CONFIDENTIAL

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88W8686

Datasheet

Doc. No. MV-S103343-00 Rev. D

CONFIDENTIAL

Page 16 Document Classification: Proprietary February 20, 2007, 2.00

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MARVELL CONFIDENTIAL, UNDER NDA# 12102018

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MARVELL CONFIDENTIAL, UNDER NDA# 12102018

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CONFIDENTIAL

Doc. No. MV-S103343-00 Rev. D

February 20, 2007, 2.00 Document Classification: Proprietary Page 17

List of Tables

Section 1. Package and Power ........................................................................................ 21

Table 1: Flip Chip Locations—280 μm Pitch...................................................................................................25

Table 2: Flip Chip Locations—500 μm Pitch...................................................................................................30

Table 3: Pin Types..........................................................................................................................................35

Table 4: WLAN RF/Network Interface ............................................................................................................35

Table 5: Baseband Interface...........................................................................................................................36

Table 6: Host Interfaces–G-SPI/SDIO ............................................................................................................38

Table 7: Bluetooth Coexistence Interface.......................................................................................................39

Table 8: EEPROM Serial Control ...................................................................................................................40

Table 9: GPIO/LED Control ............................................................................................................................40

Table 10: Joint Test Action Group (JTAG) and Test Interface..........................................................................41

Table 11: Control and Power Down..................................................................................................................42

Table 12: Power and Ground............................................................................................................................42

Table 13: Reserved ..........................................................................................................................................43

Table 14: VDD18A Supply ................................................................................................................................44

Table 15: VDD18_LDO Supply.........................................................................................................................44

Table 16: VDD30 Supply ..................................................................................................................................44

Table 17: VIO_X1 Supply .................................................................................................................................45

Table 18: VIO_X2 Supply .................................................................................................................................45

Table 19: VDD18_LDO and VDD12 Power Supply Configurations ..................................................................46

Table 20: Tri-State Floating ..............................................................................................................................47

Table 21: Output Low .......................................................................................................................................47

Table 22: Output High.......................................................................................................................................47

Section 2. Processor......................................................................................................... 49

Table 23: DMA Registers..................................................................................................................................51

Table 24: Interrupt Register (IRQ and FIQ) Mapping in Interrupt Controller Unit .............................................57

Table 25: Configuration Pins ............................................................................................................................60

Section 3. Network Functions.......................................................................................... 61

Table 26: MAC Timing Intervals .......................................................................................................................65

Table 27: QoS Queues .....................................................................................................................................67

Table 28: 802.11g Channels Supported ...........................................................................................................76

Table 29: 802.11a Channels Supported ...........................................................................................................77

Table 30: 802.11h Channels Supported ...........................................................................................................77

Table 31: 802.11j Channels Supported (Japan) ...............................................................................................78

Table 32: Mode Select......................................................................................................................................79

Table 33: RF Radio Channel Frequency Registers ..........................................................................................83

Table 34: 19.2 MHz Reference Frequency.......................................................................................................84

Table 35: 20 MHz Reference Frequency ..........................................................................................................86

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MARVELL CONFIDENTIAL, UNDER NDA# 12102018

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MARVELL CONFIDENTIAL, UNDER NDA# 12102018

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88W8686

Datasheet

Doc. No. MV-S103343-00 Rev. D

CONFIDENTIAL

Page 18 Document Classification: Proprietary February 20, 2007, 2.00

Table 36: 24 MHz Reference Frequency ......................................................................................................... 88

Table 37: 26 MHz Reference Frequency ......................................................................................................... 90

Table 38: 38.4 MHz Reference Frequency ...................................................................................................... 92

Table 39: 40 MHz Reference Frequency ......................................................................................................... 94

Table 40: CCMP/AES Registers ...................................................................................................................... 97

Table 41: TKIP/WEP Registers........................................................................................................................ 98

Table 42: BCA Registers ............................................................................................................................... 102

Table 43: Single Antenna Default Arbitration Table....................................................................................... 107

Table 44: Dual Antenna Default Arbitration Table ......................................................................................... 107

Table 45: Arbiter Decision Table (BT_FREQ_OOB Bit = 1, Always InBand)................................................. 110

Table 46: Arbiter Decision Table, Bluetooth 1.2 Device (BT_FREQ_OOB Bit = 0, Always OutofBand)........ 111

Table 47: Arbiter Decision Table, Bluetooth 1.2/1.1 Device .......................................................................... 112

Table 48: Arbitration Table Variables............................................................................................................. 112

Table 49: SM Input Ports and States ............................................................................................................. 113

Table 50: SM Port List ................................................................................................................................... 114

Section 4. Host Interfaces .............................................................................................. 115

Table 51: G-SPI Interface Description ........................................................................................................... 116

Table 52: G-SPI Interface Registers Memory Space..................................................................................... 121

Table 53: Internal SQU Memory Space ......................................................................................................... 122

Table 54: SDIO Interface Signal Description ................................................................................................. 125

Table 55: SDIO Electrical Function Definition................................................................................................ 127

Table 56: SDIO Mode, SDIO Commands ...................................................................................................... 128

Table 57: SPI Mode, SDIO Commands ......................................................................................................... 128

Table 58: SDIO Registers .............................................................................................................................. 129

Section 5. Peripheral Bus Interface............................................................................... 131

Table 59: TWSI Registers.............................................................................................................................. 133

Table 60: 1-Wire Interface Registers ............................................................................................................. 136

Table 61: SPI EEPROM Interface Description............................................................................................... 137

Table 62: Write and Read Sequence Registers............................................................................................. 138

Table 63: UART Clock Divisor ....................................................................................................................... 141

Table 64: UART Pin Definitions ..................................................................................................................... 142

Table 65: UART Boot Requirements ............................................................................................................. 142

Table 66: GPIO Functions ............................................................................................................................. 144

Section 6. Electrical Specifications............................................................................... 145

Table 67: Absolute Maximum Ratings ........................................................................................................... 145

Table 68: Operating Conditions ..................................................................................................................... 146

Table 69: Internal Operating Frequencies ..................................................................................................... 146

Table 70: DC Electricals—3V Pads (VDD30) ................................................................................................ 147

Table 71: DC Electricals—1.8V/3.3V (VIO_X1/VIO_X2)................................................................................ 147

Table 72: Thermal Conditions—68-Pin (8x8x1 mm)...................................................................................... 149

Table 73: Flip Chip Thermal Conditions—280 μm Pitch ................................................................................ 150

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Doc. No. MV-S103343-00 Rev. D

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Table 74: Flip Chip Thermal Conditions—500 μm Pitch.................................................................................150

Table 75: External Timing Requirements (RESETn Pin)................................................................................151

Table 76: Internal Reset Timing......................................................................................................................151

Table 77: Configuration Pin Serial Interface ...................................................................................................152

Table 78: DC Coupled Mode ..........................................................................................................................153

Table 79: AC Coupled Mode ..........................................................................................................................153

Table 80: Phase Noise ...................................................................................................................................153

Table 81: 19.2 MHz Clock Timing...................................................................................................................154

Table 82: 20 MHz Clock Timing......................................................................................................................154

Table 83: 24 MHz Clock Timing......................................................................................................................154

Table 84: 26 MHz Clock Timing......................................................................................................................154

Table 85: 38.4 MHz Clock Timing...................................................................................................................155

Table 86: 40 MHz Clock Timing......................................................................................................................155

Table 87: Sleep Clock Timing.........................................................................................................................156

Table 88: Crystal Specifications .....................................................................................................................156

Table 89: 802.11g/b LNA and Rx RF Mixer....................................................................................................157

Table 90: 802.11g/b RBB ...............................................................................................................................158

Table 91: 802.11a LNA and Rx RF Mixer.......................................................................................................159

Table 92: 802.11a RBB ..................................................................................................................................160

Table 93: Tx Mode..........................................................................................................................................161

Table 94: Local Oscillator ...............................................................................................................................161

Table 95: SPI Host Interface Timing Data ......................................................................................................163

Table 96: SDIO Timing Data...........................................................................................................................165

Table 97: Serial Interface Timing Data ...........................................................................................................167

Table 98: LED Mode.......................................................................................................................................168

Table 99: JTAG Timing...................................................................................................................................169

Table 100: VDD12 Current Consumption .........................................................................................................170

Table 101: VDD18A Current Consumption.......................................................................................................171

Table 102: VDD18_LDO Current Consumption................................................................................................172

Table 103: VDD30 Current Consumption .........................................................................................................173

Table 104: VIO_X1 Current Consumption ........................................................................................................173

Table 105: VIO_X2 Current Consumption ........................................................................................................174

Section 7. Part Order Numbering/Package Marking .................................................... 175

Table 106: Part Order Options..........................................................................................................................175

Appendix A. Flip Chip Underfill Requirement............................................................... 177

Table 107: Solder Bump Composition Values ..................................................................................................177

Table 108: Pad Guideline Values .....................................................................................................................180

Appendix B. Acronyms and Abbreviations................................................................... 181

Table 109: Acronyms and Abbreviations..........................................................................................................181

Appendix C. Revision History ........................................................................................ 189

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