Marvell 88W8686: 低功耗高性能Wi-Fi SoC芯片

需积分: 33 201 浏览量更新于2024-07-26 收藏 4.25MB PDF 举报

"Marvell 88W8686 是一款低成本、低功耗的集成式IEEE 802.11a/g/b MAC/基带/射频无线局域网系统级芯片（SoC），设计用于支持IEEE 802.11a或802.11g的数据速率，包括6、9、12、18、24、36、48和54 Mbps，以及802.11b的数据速率1、2、5.5和11 Mbps。此芯片由Wintech Microelectronics Co., Ltd.在中国分销，并受到NDA（非披露协议）的保护，文档编号MV-S103343-00，修订版D，发布日期为2007年2月20日。文档分类为专有封面，仅限JDK使用。" 本文档主要介绍了Marvell公司生产的88W8686芯片，它是一款专为无线局域网（WLAN）设计的高度集成的系统级芯片。该芯片符合IEEE 802.11a/g/b标准，提供了多样化的数据传输速率，以适应不同场景的需求。802.11a标准主要支持5 GHz频段的高速无线连接，而802.11g则在2.4 GHz频段提供与802.11a相近的速率，同时保持与802.11b的兼容性，确保了向后兼容性。 1. **技术特性**： - 低成本：88W8686芯片设计时考虑了成本效益，使得设备制造商能够以较低的成本实现高性能的无线网络功能。 - 低功耗：适合电池供电或对能耗有严格要求的设备，如移动设备和物联网设备。 - 高度集成：集成了MAC（媒体访问控制）、基带处理和射频功能，减少了外部组件的需求，降低了设计复杂性和体积。 - 支持多种速率：芯片支持从1 Mbps到54 Mbps的多种数据传输速率，满足不同应用需求。 2. **安全与警告**： - 文档中提到了“注意”、“警告”和“警示”等字样，表明在使用或处理该芯片时，需要注意硬件、软件的安全，防止数据丢失，以及避免个人伤害。 3. **文档管理**： - 文档状态标记为“2.00”，表示这是该文档的第2.00版本，可能有更新的修订版本存在。 - 技术出版物的版本号为0.xx，提示可能存在后续修订和更新。 - Marvell公司规定，未经许可，不得以任何形式复制或传播此文档，无论是电子还是机械方式，包括影印和录音。 Marvell 88W8686是一款面向无线网络设备的高性能SoC解决方案，它在保证性能的同时，兼顾了成本和功耗，是开发802.11a/g/b无线产品的理想选择。由于涉及到NDA，具体的芯片细节和技术规格可能需要通过与Marvell公司或其授权分销商进一步接触来获取。

88W8686

Datasheet

Doc. No. MV-S103343-00 Rev. D

CONFIDENTIAL

Page 16 Document Classification: Proprietary February 20, 2007, 2.00

THIS PAGE INTENTIONALLY LEFT BLANK

CONFIDENTIAL

Doc. No. MV-S103343-00 Rev. D

February 20, 2007, 2.00 Document Classification: Proprietary Page 17

List of Tables

Section 1.Package and Power........................................................................................ 21

Table 1: Flip Chip Locations—280 μm Pitch...................................................................................................25

Table 2: Flip Chip Locations—500 μm Pitch...................................................................................................30

Table 3: Pin Types..........................................................................................................................................35

Table 4: WLAN RF/Network Interface............................................................................................................35

Table 5: Baseband Interface...........................................................................................................................36

Table 6: Host Interfaces–G-SPI/SDIO............................................................................................................38

Table 7: Bluetooth Coexistence Interface.......................................................................................................39

Table 8: EEPROM Serial Control...................................................................................................................40

Table 9: GPIO/LED Control............................................................................................................................40

Table 10: Joint Test Action Group (JTAG) and Test Interface..........................................................................41

Table 11: Control and Power Down..................................................................................................................42

Table 12: Power and Ground............................................................................................................................42

Table 13: Reserved..........................................................................................................................................43

Table 14: VDD18A Supply................................................................................................................................44

Table 15: VDD18_LDO Supply.........................................................................................................................44

Table 16: VDD30 Supply..................................................................................................................................44

Table 17: VIO_X1 Supply.................................................................................................................................45

Table 18: VIO_X2 Supply.................................................................................................................................45

Table 19: VDD18_LDO and VDD12 Power Supply Configurations..................................................................46

Table 20: Tri-State Floating..............................................................................................................................47

Table 21: Output Low.......................................................................................................................................47

Table 22: Output High.......................................................................................................................................47

Section 2.Processor......................................................................................................... 49

Table 23: DMA Registers..................................................................................................................................51

Table 24: Interrupt Register (IRQ and FIQ) Mapping in Interrupt Controller Unit.............................................57

Table 25: Configuration Pins............................................................................................................................60

Section 3.Network Functions.......................................................................................... 61

Table 26: MAC Timing Intervals.......................................................................................................................65

Table 27: QoS Queues.....................................................................................................................................67

Table 28: 802.11g Channels Supported...........................................................................................................76

Table 29: 802.11a Channels Supported...........................................................................................................77

Table 30: 802.11h Channels Supported...........................................................................................................77

Table 31: 802.11j Channels Supported (Japan)...............................................................................................78

Table 32: Mode Select......................................................................................................................................79

Table 33: RF Radio Channel Frequency Registers..........................................................................................83

Table 34: 19.2 MHz Reference Frequency.......................................................................................................84

Table 35: 20 MHz Reference Frequency..........................................................................................................86

88W8686

Datasheet

Doc. No. MV-S103343-00 Rev. D

CONFIDENTIAL

Page 18 Document Classification: Proprietary February 20, 2007, 2.00

Table 36: 24 MHz Reference Frequency.........................................................................................................88

Table 37: 26 MHz Reference Frequency.........................................................................................................90

Table 38: 38.4 MHz Reference Frequency......................................................................................................92

Table 39: 40 MHz Reference Frequency.........................................................................................................94

Table 40: CCMP/AES Registers......................................................................................................................97

Table 41: TKIP/WEP Registers........................................................................................................................98

Table 42: BCA Registers...............................................................................................................................102

Table 43: Single Antenna Default Arbitration Table.......................................................................................107

Table 44: Dual Antenna Default Arbitration Table.........................................................................................107

Table 45: Arbiter Decision Table (BT_FREQ_OOB Bit = 1, Always InBand).................................................110

Table 46: Arbiter Decision Table, Bluetooth 1.2 Device (BT_FREQ_OOB Bit = 0, Always OutofBand)........111

Table 47: Arbiter Decision Table, Bluetooth 1.2/1.1 Device..........................................................................112

Table 48: Arbitration Table Variables.............................................................................................................112

Table 49: SM Input Ports and States.............................................................................................................113

Table 50: SM Port List...................................................................................................................................114

Section 4.Host Interfaces.............................................................................................. 115

Table 51: G-SPI Interface Description...........................................................................................................116

Table 52: G-SPI Interface Registers Memory Space.....................................................................................121

Table 53: Internal SQU Memory Space.........................................................................................................122

Table 54: SDIO Interface Signal Description.................................................................................................125

Table 55: SDIO Electrical Function Definition................................................................................................127

Table 56: SDIO Mode, SDIO Commands......................................................................................................128

Table 57: SPI Mode, SDIO Commands.........................................................................................................128

Table 58: SDIO Registers..............................................................................................................................129

Section 5.Peripheral Bus Interface............................................................................... 131

Table 59: TWSI Registers..............................................................................................................................133

Table 60: 1-Wire Interface Registers.............................................................................................................136

Table 61: SPI EEPROM Interface Description...............................................................................................137

Table 62: Write and Read Sequence Registers.............................................................................................138

Table 63: UART Clock Divisor.......................................................................................................................141

Table 64: UART Pin Definitions.....................................................................................................................142

Table 65: UART Boot Requirements.............................................................................................................142

Table 66: GPIO Functions.............................................................................................................................144

Section 6.Electrical Specifications............................................................................... 145

Table 67: Absolute Maximum Ratings...........................................................................................................145

Table 68: Operating Conditions.....................................................................................................................146

Table 69: Internal Operating Frequencies.....................................................................................................146

Table 70: DC Electricals—3V Pads (VDD30)................................................................................................147

Table 71: DC Electricals—1.8V/3.3V (VIO_X1/VIO_X2)................................................................................147

Table 72: Thermal Conditions—68-Pin (8x8x1mm)......................................................................................149

Table 73: Flip Chip Thermal Conditions—280 μm Pitch................................................................................150

CONFIDENTIAL

Doc. No. MV-S103343-00 Rev. D

February 20, 2007, 2.00 Document Classification: Proprietary Page 19

Table 74: Flip Chip Thermal Conditions—500 μm Pitch.................................................................................150

Table 75: External Timing Requirements (RESETn Pin)................................................................................151

Table 76: Internal Reset Timing......................................................................................................................151

Table 77: Configuration Pin Serial Interface...................................................................................................152

Table 78: DC Coupled Mode..........................................................................................................................153

Table 79: AC Coupled Mode..........................................................................................................................153

Table 80: Phase Noise...................................................................................................................................153

Table 81: 19.2 MHz Clock Timing...................................................................................................................154

Table 82: 20 MHz Clock Timing......................................................................................................................154

Table 83: 24 MHz Clock Timing......................................................................................................................154

Table 84: 26 MHz Clock Timing......................................................................................................................154

Table 85: 38.4 MHz Clock Timing...................................................................................................................155

Table 86: 40 MHz Clock Timing......................................................................................................................155

Table 87: Sleep Clock Timing.........................................................................................................................156

Table 88: Crystal Specifications.....................................................................................................................156

Table 89: 802.11g/b LNA and Rx RF Mixer....................................................................................................157

Table 90: 802.11g/b RBB...............................................................................................................................158

Table 91: 802.11a LNA and Rx RF Mixer.......................................................................................................159

Table 92: 802.11a RBB..................................................................................................................................160

Table 93: Tx Mode..........................................................................................................................................161

Table 94: Local Oscillator...............................................................................................................................161

Table 95: SPI Host Interface Timing Data......................................................................................................163

Table 96: SDIO Timing Data...........................................................................................................................165

Table 97: Serial Interface Timing Data...........................................................................................................167

Table 98: LED Mode.......................................................................................................................................168

Table 99: JTAG Timing...................................................................................................................................169

Table 100: VDD12 Current Consumption.........................................................................................................170

Table 101: VDD18A Current Consumption.......................................................................................................171

Table 102: VDD18_LDO Current Consumption................................................................................................172

Table 103: VDD30 Current Consumption.........................................................................................................173

Table 104: VIO_X1 Current Consumption........................................................................................................173

Table 105: VIO_X2 Current Consumption........................................................................................................174

Section 7.Part Order Numbering/Package Marking.................................................... 175

Table 106: Part Order Options..........................................................................................................................175

Appendix A.Flip Chip Underfill Requirement............................................................... 177

Table 107: Solder Bump Composition Values..................................................................................................177

Table 108: Pad Guideline Values.....................................................................................................................180

Appendix B.Acronyms and Abbreviations................................................................... 181

Table 109: Acronyms and Abbreviations..........................................................................................................181

Appendix C.Revision History........................................................................................ 189

剩余189页未读，继续阅读

无根的水

粉丝: 5
资源: 35

Marvell 88W8686: 低功耗高性能Wi-Fi SoC芯片

Marvell 88w8686手册及linux下驱动

marvell 88w8686 芯片datasheet 无水印完整版

Marvell 88w8787 Datasheet

marvell 88x3310 代理 datasheet

marvell 88e6176 datasheet

88se9215 datasheet

88e1116r_datasheet

88e6390 datasheet

88e1119r-nnw2 datasheet

88W8686系统基带处理

最新资源