从x86到x64：64位计算机编程入门指南
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更新于2024-08-25
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"《x64 Assembly入门指南》是由Chris Lomont于2009年发布的一份文档，旨在帮助那些从传统的x86汇编转向64位平台的程序员。随着32位个人计算机逐渐被64位系统取代，x86汇编语言的基础发生了变化。该教程以一种易于理解的方式介绍了x64汇编，即使没有x86汇编经验的读者也能从中受益，它将有助于平滑地过渡到新的技术栈。
x64是英特尔和AMD针对32位x86指令集架构（ISA）扩展的通用术语。AMD首先推出了x86-64版本，后来改称为AMD64，而英特尔则将其实现称为IA-32e和EMT64。尽管两者之间存在细微的不兼容性，但大部分代码在两种版本上都能正常运行，具体差异可以在各自的手册中找到，这些共同的部分被称为x64架构。
x64汇编不应与英特尔的Itanium 64位架构混淆，后者被称为IA-64。本文将重点放在软件层面，不涉及硬件细节如缓存、分支预测等高级主题。文章最后会提供一系列参考文献，供读者进一步深入学习硬件相关知识和进阶主题。
在计算机科学领域，x64汇编仍然被用于编写对性能要求极高的程序，尤其是在操作系统、驱动程序和游戏开发等领域。通过掌握x64汇编，程序员可以充分利用现代处理器的特性，优化代码执行效率。对于想要深入了解底层系统编程或希望在64位平台上进行专业开发的人来说，这份指南是一份宝贵的资源。"
There are odd limitations accessing the byte registers
due to coding issues in the REX opcode
prefix used for the new registers: an instruction cannot reference a legacy high byte (AH, BH,
CH, DH) and one of the new byte registers at the same time (such as R11B) but it can use legacy
low bytes (AL, BL, CL, DL). This is enforced by changing (AH, BH, CH, DH) to (BPL, SPL,
DIL, SIL) for instructions using a REX prefix.
The 64-bit instruction pointer RIP points to the next instruction to be executed, and supports a
64-bit flat memory model. Memory address layout in current operating systems is covered later.
The stack pointer RSP points to the last item pushed onto the stack, which grows toward lower
addresses. The stack is used to store return addresses for subroutines, for passing parameters in
higher level languages such as C/C++, and for storing “shadow space” covered in calling
conventions.
The RFLAGS register stores flags used for results of operations and for controlling the
processor. This is formed from the x86 32-bit register EFLAGS by adding a higher 32 bits which
are reserved and currently unused. Table 1 lists the most useful flags. Most of the other flags are
used for operating system level tasks and should always be set to the value previously read.
Table 1 – Common Flags
Symbol
Bit
Name
Set if….
CF
0
Carry
Operation generated a carry or borrow
PF
2
Parity
Last byte has even number of 1‟s, else 0
AF
4
Adjust
Denotes Binary Coded Decimal in-byte carry
ZF
6
Zero
Result was 0
SF
7
Sign
Most significant bit of result is 1
OF
11
Overflow
Overflow on signed operation
DF
10
Direction
Direction string instructions operate (increment or decrement)
ID
21
Identification
Changeability denotes presence of CPUID instruction
The floating point unit (FPU) contains eight registers FPR0-FPR7, status and control registers,
and a few other specialized registers. FPR0-7 can each store one value of the types shown in
Table 2. Floating point operations conform to IEEE 754. Note that most C/C++ compilers
support the 32 and 64 bit types as float and double, but not the 80-bit one available from
assembly. These registers share space with the eight 64-bit MMX registers.
Table 2 – Floating Point Types
Data Type
Length
Precision
(bits)
Decimal digits
Precision
Decimal Range
Single Precision
32
24
7
1.18*10^-38 to 3.40*10^38
Double Precision
64
53
15
2.23 *10^-308 to 1.79*10^308
Extended Precision
80
64
19
3.37*10^-4932 to 1.18*10^4932
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