TPS2492
TPS2493
www.ti.com
SLUSA65C –JULY 2010–REVISED JANUARY 2013
DETAILED PIN DESCRIPTION
The following description relies on the Typical Application Diagram shown on page 1, and the Functional Block
Diagram.
VCC: This pin is associated with three functions:
1. Biasing power to the integrated circuit,
2. Input to power on reset (POR) and under-voltage lockout (UVLO) functions, and
3. Voltage sense at one terminal of R
SENSE
for M1 current measurement.
The voltage must exceed the POR (about 6 V for roughly 400 µs) and the internal UVLO (about 8 V) before
normal operation (driving the GATE) may begin. Connections to VCC should be designed to minimize R
SENSE
voltage sensing errors and to maximize the effect of C1 and D1; place C1 at R
SENSE
rather than at the device pin
to eliminate transient sensing errors. GATE, PROG, and TIMER are held low when either UVLO or POR are
active. PG and FLT are open drain when either UVLO or POR are active.
SENSE: Monitors the voltage at the drain of M1, and the downstream side of R
SENSE
providing the constant
power limit engine with feedback of both M1 current (I
D
) and voltage (V
DS
). Voltage is determined by the
difference between SENSE and OUT, while the current analog is the voltage difference between VCC and
SENSE. The constant power engine uses V
DS
to compute the allowed I
D
and is clamped to 50 mV, acting like a
traditional current limit at low V
DS
. The current limit is set by the following equation:
(1)
Design the connections to SENSE to minimize R
SENSE
voltage sensing errors. Don't drive SENSE to a large
voltage difference from VCC because it is internally clamped to VCC. The current limit function can be disabled
by connecting SENSE to VCC.
GATE: Provides the high side (above VCC) gate drive for external N-channel FET. It is controlled by the internal
gate drive amplifier, which provides a pull-up of 22 µA from an internal charge pump and both strong (125 mA)
and weak (2 mA) pull-downs to ground. The strong pull down is triggered by an overvoltage on the OV pin or
large overcurrent to the load. The strong pull-down current is a non-linear function of the gate amplifier overdrive;
it provides small drive for small overloads, but large overdrive for fast reaction to an output short. There is a
separate pull-down of 2 mA to shut the MOSFET off when UVEN or UVLO cause this to happen. If an output
short causes the VCC to fall below the UVLO, the turnoff speed will be limited by the 2mA turnoff current. An
internal clamp protects the gate of the FET (to OUT).
OUT: This input pin is used by the constant power engine and the PG comparator to measure V
DS
of M1 as
V
(SENSE-OUT)
. Internal protection circuits leak a small current from this pin when it is low. If the load circuit can
drive OUT below ground, connect a clamp (or freewheel) diode from OUT (cathode) to GND (anode). The diode
should clamp the output above -1 V during the transient.
UVEN: The positive threshold of UVEN must be exceeded before the GATE driver is enabled. If the UVEN pin
drops below the UVEN negative threshold while the GATE driver is enabled, the GATE driver will be pulled to
GND by the 2-mA pull down. UVEN can be used as a logic control input, an analog input voltage monitor as
illustrated by R1, R2 and R3 in the Typical Application Circuit, or it can be tied to VCC to always enable the
TPS2492/3. The hysteresis associated with the internal comparator makes this a stable method of detecting a
low input condition and shutting the downstream circuits off. A TPS2492 that has latched off can be reset by
cycling UVEN below its negative threshold and back high.
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