Atheros AR9582单芯片2x2 MIMO无线路由器datasheet

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Atheros AR9582数据手册提供了关于这款高度集成的单芯片解决方案的详细信息，适用于2.4 GHz或5 GHz的802.11n无线局域网络（WLAN）。该芯片设计旨在实现高性能的2x2多输入多输出（MIMO）无线通信，通过PCI Express接口与系统主板连接，为现代无线设备提供高速无线传输和连接能力。 AR9582的主要特点包括： 1. **集成度高**：作为单一芯片解决方案，AR9582集成了基带（BB）、射频（RF）和MAC功能于一身，简化了硬件设计并降低了系统复杂性。 2. **支持频率范围**：兼容2.4 GHz和5 GHz频段，覆盖广泛的应用场景，如家庭、办公室或商业环境中的Wi-Fi网络。 3. **2x2 MIMO技术**：采用双流MIMO架构，允许同时处理两个独立的数据流，显著提升数据传输速率和网络效率，特别是在多用户环境中。 4. **PCI Express接口**：通过高速PCIe接口与系统连接，能够快速传输数据，支持更高的吞吐量和低延迟，适合对性能要求高的应用。 5. **802.11n标准**：符合IEEE 802.11n标准，提供理论上的最高数据速率达到450Mbps（2x2配置下），这在当时是无线通信技术的一个重要里程碑。 6. **商标和知识产权**：Atheros公司拥有多项注册商标，如Atheros SST（信号持久技术）、Ethos、Simpli-Fi等，体现了其在无线通信领域的技术优势。 7. **专利技术**：文档中提到的其他技术如Signal-SustainTechnology、InstallNGo、ique、ROCm等都是Atheros的创新成果，表明AR9582具有独特的性能优化和易用性。 8. **时间戳**：该数据手册更新日期为2011年12月，反映了当时的最新技术和规格，但可能不包含后续的软件更新或硬件改进。 9. **版权声明**：所有权利保留，未经许可不得复制或分发，且内容可能会根据需要进行无通知变更。 AR9582是一款专为高性能2.4 GHz和5 GHz 802.11n WLAN设计的单芯片解决方案，通过集成的MIMO技术、PCI Express接口和多项Atheros专利技术，为用户提供高速、可靠和灵活的无线连接体验。对于需要构建高级无线网络应用的工程师和系统设计师来说，这款芯片是一个重要的参考资源。

16 • AR9582 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs Atheros Communications, Inc.

16 • December 2011 COMPANY CONFIDENTIAL

Atheros Communications, Inc. AR9582 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs • 17

COMPANY CONFIDENTIAL December 2011 • 17

2. Functional Description

2.1 Overview

The AR9582 consists of four major functional

blocks: PCI Express interface, MAC, digital

PHY, and radio.

The IEEE 802.11 MAC functionality is

partitioned between the host and the AR9582.

IEEE 802.11 MAC data service is provided by

the MAC of the AR9582, while the host

software, with the aid of the AR9582 MAC,

controls Tx and Rx queue processing.

The baseband digital processing functions are

implemented by the digital PHY of the

AR9582. The radio frequency (RF) and

baseband analog processing are provided by

the integrated radio. The physical layer (PHY)

is partitioned between the baseband processor

and the radio. The configuration block, PLL,

ADC, DAC, EEPROM interface, JTAG, antenna

control, and GPIO complete the AR9582

functionality. See Figure 2-1.

2.1.1 Configuration Block

The configuration block provides control,

status, and configuration, for each major

functional block. This block contains registers

accessed by other blocks and by the host using

the PCI Express interface.

2.1.2 AR9582 Address MAP

Internal registers of the various functional

blocks and the AR9582 peripheral interface are

accessible with the host using the PCI Express

interface. These register locations are defined

as offset addresses. The combination of the host

base address and the offset address allows

access to a particular internal register. Table 2-1

lists the offset addresses for the AR9582

internal registers and peripheral interface.

Figure 2-1. Functional Block Diagram of the AR9582

Table 2-1. Offset Addresses

Offset Address Range Usage Description

0x0000–0x07FC MAC DMA general DMA access

0x0800–0x0FFC MAC DMA QCU registers Control and status register for QCU

0x1000–0x1FFC MAC DMA DCU registers Control and status register for DCU

0x2000–0x3FFC EEPROM access register Memory location of EEPROM are mapped to this

address range and allow access to EEPROM

0x4000–0x4FFC Host interface Control and status register for host interface

0x8000–0x98FC MAC PCU registers Control and status register for PCU

18 • AR9582 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs Atheros Communications, Inc.

18 • December 2011 COMPANY CONFIDENTIAL

2.1.3 On-Chip One-Time Programmable (OTP)

Memory

The AR9582 provides OTP memory for storing

calibration data to eliminate the need for an

external EEPROM. The hardware detects

whether an external EEPROM is present. If

none is present, it sets bit [8] of the “EEPROM

Control (HOST_INTF_EEPROM_CTRL)”

2.1.4 Serial EEPROM Interface

The AR9582 provides a serial interface to access

an external EEPROM. The EEPROM interface

modifies configuration space registers and

configuration- and vendor-specific

information.

The off-chip EEPROM can be:

■

A 32-Kb device, organized as 2,048 entries

of 16 bits each (2,048x16)

■

An 64-Kb device, organized as 4,096 entries

of 16 bits each (4,096x16)

The hardware automatically detects EEPROM

size. The EEPROM addressing is 16 bits wide,

with each 16-bit EEPROM mapped into the

AR9582's register space. Each 32-bit aligned

address corresponds to a unique EEPROM

location. Because the host interface supports

32-bit register accesses and ignores the two

least significant address bits, the address offset

provided by the host interface corresponds to

four times the EEPROM location.

At reset, some PCI Express configuration

registers load from the EEPROM while others

are programmed by the host or initialized by

AR9582 hardware. To ensure that the EEPROM

contents are valid, a 16-bit word at address

offset 0x2000 is checked. If the values do not

match 0xA55A, the EEPROM contents are

ignored and the default values loaded.

2.1.5 EEPROM Auto-Sizing Mechanism

The first procedure after reset is to read the

offset address 0x2000 to check for the content

0xA55A. The EEPROM physical presence,

programmed state, and size are determined

automatically. If the offset address 0x2000

contents do not match the 0xA55A value for

any supported EEPROM sizes, the AR9582

assumes the EEPROM is not present on the

PCB, or is present but not programmed. In

either case, the logic uses the default values as

described in “Serial EEPROM Interface”.

2.1.6 EEPROM Read/Write Protection

Mechanism

The EEPROM contains a 16-bit word protect

mask value at address location 0x2010H that

prevents software from accessing certain

regions. The mask is 16 bits wide and contains

eight sub-masks that are 2 bits wide.

The sub-mask can have four values that

determine the access types permitted to the

associated protection region:

■

00: Read/write access allowed

■

01: Write-only access allowed

■

10: Read-only access allowed

■

11: No access allowed

2.2 Reset

The RESET_L pin controls the AR9582 chip

reset. The AR9582 host interface receives two

reset signals as below:

■

RESET_L pin

Controls the AR9582 power reset

■

PCIE_RST_L

Controls the PCI Express core reset

In addition, the real-time clock (RTC) reset

reset for the MAC/baseband and PCU blocks.

See the register “RTC Reset and Force Sleep

and Force Wakeup (RTC_RESET)” on page 108.

2.3 GPIO

The AR9582 provides 13 configurable bi-

directional general purpose I/O ports and 1

configurable input-only port. Each GPIO port

can be configured independently as input or

output using the GPIO control registers.

Information presented at GPIO inputs and

outputs can be read from the “GPIO Output

(HOST_INTF_GPIO_OUT)” and “GPIO Input

(HOST_INTF_GPIO_IN)” registers.

In addition, Bluetooth coexistence functions

can also map to GPIO10, GPI9, and GPIO[7:0].

See the “GPIO Input MUX1

(HOST_INTF_GPIO_INPUT_MUX1)” and

“GPIO Input MUX2

(HOST_INTF_GPIO_INPUT_MUX2)”

registers. Table 6-14 on page 102 lists the

functionalities that can map to GPIO outputs

using the “GPIO Output MUX1

(HOST_INTF_GPIO_OUTPUT_MUX1)”,

“GPIO Output MUX2

(HOST_INTF_GPIO_OUTPUT_MUX2)”, and

“GPIO Output MUX3

(HOST_INTF_GPIO_OUTPUT_MUX3)”

registers.

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