3D IC集成：TSV互连技术在内存模块封装中的发展

需积分: 9 27 浏览量更新于2024-09-13 1 收藏 2.82MB PDF 举报

"这篇文档是关于在内存模块flip chip封装中开发硅通孔(TSV)中介层的研究。由Nicholas Kao, Eason Chen, Daniel Lee和Mike Ma等人撰写，来自Siliconware Precision Industries Co., Ltd.的先进产品设计与测试部门。文中探讨了3D集成系统级封装(SiP)中，如何利用TSV中介层技术实现高密度和异构集成，以应对微电子封装领域对更高功能、更强性能和更小尺寸的需求。同时，文章指出由于材料热膨胀系数(CTE)的差异，在TSI制造过程中可能会引发热机械应力和翘曲，可能导致TSV或控制塌陷芯片连接(C4)凸块的裂纹问题，这是TSI与有机基板键合后的主要挑战。" 在微电子封装领域，随着对设备功能、性能和小型化需求的不断提高，传统的封装方式已经难以满足这些要求。"Development of TSV interposer for flipchip package"这一主题揭示了研究者们正在探索通过硅通孔(TSV)中介层技术来解决这一问题。TSV技术是一种3D集成方案，它允许在硅片内部创建垂直互连，从而实现更高密度的封装，并能将不同类型的芯片（异构集成）整合在同一封装内。 TSV中介层在内存模块的flip chip封装中扮演着关键角色，因为它提供了大量的输入/输出(I/O)连接，同时保持了良好的电气特性。Flip chip封装技术使得芯片能够直接面朝下放置在基板上，通过控制塌陷芯片连接(C4)实现电气接触，这有助于减小封装尺寸并提高性能。然而，TSV中介层的引入也带来了新的挑战，尤其是在热管理和机械稳定性方面。由于TSV中介层材料与周围材料之间存在热膨胀系数(CTE)的差异，这会在制造过程中产生热机械应力，导致TSV自身或C4凸块发生裂纹。这种现象可能影响封装的可靠性和整体性能。因此，研究者必须对TSI制造过程进行优化，包括TSV的制备工艺和TSI与有机基板的键合技术，以降低应力和翘曲，确保封装的稳定性和可靠性。此外，解决这些问题可能涉及到材料选择、封装设计优化、热管理策略以及先进的检测和模拟技术。通过这些方法，可以减轻或消除由于CTE不匹配导致的负面影响，实现高效、可靠的TSV中介层封装技术，以满足未来微电子设备的高性能和小型化需求。

Development of Through Silicon Via (TSV) Interposer for

Memory Module Flip Chip Package

Nicholas Kao, Eason Chen, Daniel Lee, Mike Ma

Advanced Product Design & Testing Dept. Corporate R & D, Siliconware Precision Industries Co. Ltd.

No. 123, Sec. 3, Da Fong Rd, Tantzu, Taichung 42749, Taiwan, R.O.C.

Email: nicholas@spil.com.tw

Tel: 886-4-25341525 ext 7941

Abstract

With the trend of microelectronics packaging toward

more functionality, high performance and smaller form

factor, the product is required to deliver more I/Os and better

electrical characteristics under a minimum module system.

Therefore, a 3D IC integration System in Package (SiP) with

passive Through Silicon Via (TSV) interposer technology is

proposed to provide high density and heterogeneous

integration needed for such requirement.

Due to the Coefficients of Thermal Expansion (CTE)

mismatch between materials, thermal-mechanical stress and

warpage are induced during Through Silicon Interposer (TSI)

fabrication process, which may affect TSV crack or

Controlled Collapse Chip Connection (C4) bump crack after

TSI bonding to organic substrate process. Therefore, this

work is a step by step process simulation with various design

parameters by finite element method (FEM) to investigate

stress and warpage behaviors of processing effect. For both

full array dummy bumps layout and thinner top chips are to

reduce micro-bump stress. Also, low CTE organic substrate

core, high CTE mold compound and thinner top chips

perform lower package warpage. Finally, this paper aims to

provide a guideline to designer for 3D IC integration SiP

with passive TSV interposer structure by using the finite

element models.

Introduction

As the demands of more functionality and high

performance, the product is required to deliver more I/Os and

better electrical characteristics. Therefore, a 3D IC

integration package with TSI technology is proposed to

provide high density and heterogeneous integration needed

for such requirement. Functional chips stacked on a TSI then

assembled on an organic substrate is as test vehicle (See

Figure-1). The electrical connection between functional chips

to TSI is through micro-bumps and Re-Distribution Layer

(RDL) then is going to the TSV of TSI. TSI and organic

substrate interconnect is by C4 bumps. Due to the CTE

mismatch between materials, thermal-mechanical stress and

warpage are induced during TSI fabrication and package

assembly process, which may affect TSV crack or C4 bump

crack after top chips bonding to TSI and TSI bonding to

organic substrate processes.

Firstly, the design parameters including RDL design, TSI

thickness, bump layout, top chip thickness and DRAM chips

space are discussed in detail. The key challenge during

assembly process is chip level warpage contribution to cause

solder bump non-wetting or bridge issue. From simulation

result, a balanced RDL Cu coverage design is effective to

reduce TSI warpage. In addition, thinner top chip thickness

with full array dummy bump layout performs lower micro-

bump stress. Secondly, the underfill, mold compound and

organic substrate core material selection are also included in

this paper. In assembly flow, top chips are assembled on TSI

and filled the micro-bump gap with underfill, then entire

package and C4 bump gap are filled with mold compound.

The simulation indicated that low CTE core and high CTE

compound are effective to reduce package warpage. Finally,

this paper aims to provide a guideline to designer for 3D IC

integration SiP with passive TSV interposer structure by

using the finite element models.

(a)

(b)

Figure-1: 3D FCCSP test vehicle. (a) side view (b) top view.

Test Vehicle

Figure-1 shows a multi-chip stacked 3D-FCCSP test

vehicle used in this paper. This structure consists of three top

chips with lead free micro-bumps and a bottom TSI with lead

free C4 bumps. Top chips include two DRAM chips and one

SOC chip with the size of 7.74mm  6.24mm and 6.98mm 

6.73mm, respectively. They were stacked on a TSI with the

size of 16.0mm  14.6mm. Then, underfill was filled into the

gap between top chips and TSI which is around micro-

bumps. After chip to chip stacking process, it was stacked on

an organic substrate and jointed by C4 bumps. The entire

package and C4 bump gap was filled with mold compound.

Detail package size and dimension are summarized in Table-

下载后可阅读完整内容，剩余5页未读，立即下载

fangsnan

粉丝: 0
资源: 1

3D IC集成：TSV互连技术在内存模块封装中的发展

Electrical transmission characteristics of differential TSV structures in 3D TSV packaging

Simplified Empirical Formula on TSV Thermal Analysis for 3D IC EDA

tsv-train

TSV信道模型

pacifier.tsv

TSV封装技术

gapminder.tsv

sublime_rainbow_csv：彩虹CSV-Sublime Text Package：突出显示CSV和TSV文件中的列并以类似SQL的语言运行查询

Analytical Model of Internal Heat Transfer of aPower Chip with Through Silicon Via

matlab tsv

最新资源