Stellaris LM3S5P36 Cortex-M3 微控制器DataSheet

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"lm3s5p36 DataSheet - Cortex-M3 lm3s5p36 芯片的技术规格说明书" 《Stellaris LM3S5P36 Microcontroller DataSheet》是德州仪器（Texas Instruments）发布的一份关于其微控制器产品的详细技术文档。这份 datasheet 涵盖了Cortex-M3架构的LM3S5P36芯片的相关信息，该芯片是Stellaris系列的一部分。Stellaris和StellarisWare是德州仪器的注册商标，而ARM、Thumb则是ARMLimited的注册商标，Cortex是其商标。该文档提供了关于LM3S5P36微控制器的先进技术信息，适用于产品处于取样或预生产阶段。由于是先进信息，文档中的特性数据和其他规格可能在未经通知的情况下发生变化，因此在设计过程中需要密切关注更新。 LM3S5P36芯片基于高效的Cortex-M3内核，这是一种32位RISC处理器，专为低功耗应用设计。它通常被用于嵌入式系统，如工业控制、消费电子和汽车电子等领域。Cortex-M3内核提供了高性能和低功耗的平衡，适合各种实时应用。 datasheet中可能包含以下关键内容： 1. **概述**：介绍LM3S5P36芯片的主要特点，如处理能力、内存配置、外设接口等。 2. **硬件特性**：包括CPU时钟速度、闪存大小、SRAM容量、GPIO引脚数量以及其他外设接口，如UART、SPI、I2C、PWM等。 3. **电源管理**：描述芯片的电源选项和低功耗模式，以及如何有效地管理和控制能耗。 4. **外设接口**：详述各种内置外设的功能和操作，这些接口是系统与外部设备通信的关键。 5. **封装和引脚配置**：提供芯片封装信息和引脚布局，以便于硬件设计和PCB布局。 6. **开发工具和支持**：可能提及TI提供的开发板、IDE、编译器和调试工具，以及获取技术支持的途径。 7. **电气特性**：包括电压范围、工作温度范围、电流消耗等电气参数。 8. **应用示例**：可能包含一些典型应用案例，展示芯片如何应用于实际项目。 9. **安全和警告**：强调使用TI半导体产品时的重要注意事项，特别是对于关键应用的标准保修和免责声明。由于此文档的详细内容没有完全提供，以上只是一般性的概述。在实际应用中，工程师会根据 datasheet 提供的具体信息来设计和优化系统，确保软件和硬件的兼容性以及系统的可靠性和性能。访问德州仪器的官方网站或指定支持链接可以获取完整的LM3S5P36 DataSheet，以获取所有必要的详细信息。

Table 18-1. Signals for Analog Comparators (64LQFP) .......................................................... 860

Table 18-2. Internal Reference Voltage and ACREFCTL Field Values ..................................... 862

Table 18-3. Analog Comparators Register Map ..................................................................... 863

Table 19-1. Signals for PWM (64LQFP) ................................................................................ 874

Table 19-2. PWM Register Map ............................................................................................ 881

Table 20-1. Signals for QEI (64LQFP) ................................................................................... 943

Table 20-2. QEI Register Map .............................................................................................. 947

Table 22-1. GPIO Pins With Default Alternate Functions ........................................................ 965

Table 22-2. Signals by Pin Number ....................................................................................... 966

Table 22-3. Signals by Signal Name ..................................................................................... 971

Table 22-4. Signals by Function, Except for GPIO ................................................................. 976

Table 22-5. GPIO Pins and Alternate Functions ..................................................................... 981

Table 22-6. Possible Pin Assignments for Alternate Functions ................................................ 983

Table 22-7. Connections for Unused Signals (64-Pin LQFP) ................................................... 984

Table 23-1. Temperature Characteristics ............................................................................... 986

Table 23-2. Thermal Characteristics ..................................................................................... 986

Table 23-3. ESD Absolute Maximum Ratings ........................................................................ 986

Table 24-1. Maximum Ratings .............................................................................................. 987

Table 24-2. Recommended DC Operating Conditions ............................................................ 987

Table 24-3. JTAG Characteristics ......................................................................................... 988

Table 24-4. Power Characteristics ........................................................................................ 990

Table 24-5. Reset Characteristics ......................................................................................... 991

Table 24-6. LDO Regulator Characteristics ........................................................................... 992

Table 24-7. Phase Locked Loop (PLL) Characteristics ........................................................... 992

Table 24-8. Actual PLL Frequency ........................................................................................ 993

Table 24-9. PIOSC Clock Characteristics .............................................................................. 993

Table 24-10. 30-kHz Clock Characteristics .............................................................................. 993

Table 24-11. Hibernation Clock Characteristics ....................................................................... 993

Table 24-12. HIB Oscillator Input Characteristics ..................................................................... 994

Table 24-13. Main Oscillator Clock Characteristics .................................................................. 994

Table 24-14. Supported MOSC Crystal Frequencies ................................................................ 994

Table 24-15. System Clock Characteristics with ADC Operation ............................................... 995

Table 24-16. Sleep Modes AC Characteristics ......................................................................... 995

Table 24-17. Hibernation Module Battery Characteristics ......................................................... 995

Table 24-18. Hibernation Module AC Characteristics ............................................................... 996

Table 24-19. Flash Memory Characteristics ............................................................................ 997

Table 24-20. GPIO Module Characteristics ............................................................................. 997

Table 24-21. ADC Characteristics ........................................................................................... 998

Table 24-22. ADC Module External Reference Characteristics ................................................. 999

Table 24-23. ADC Module Internal Reference Characteristics .................................................. 999

Table 24-24. SSI Characteristics ............................................................................................ 999

Table 24-25. I

C Characteristics ........................................................................................... 1001

Table 24-26. 100BASE-TX Transmitter Characteristics .......................................................... 1002

Table 24-27. 100BASE-TX Transmitter Characteristics (informative) ....................................... 1002

Table 24-28. 100BASE-TX Receiver Characteristics .............................................................. 1002

Table 24-29. 10BASE-T Transmitter Characteristics .............................................................. 1002

Table 24-30. 10BASE-T Transmitter Characteristics (informative) ........................................... 1003

Table 24-31. 10BASE-T Receiver Characteristics .................................................................. 1003

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Table of Contents

List of Registers

The Cortex-M3 Processor ............................................................................................................. 65

Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 72

Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 72

Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 72

Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 72

Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 72

Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 72

Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 72

Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 72

Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 72

Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 72

Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 72

Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 72

Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 72

Register 14: Stack Pointer (SP) ........................................................................................................... 73

Register 15: Link Register (LR) ............................................................................................................ 74

Register 16: Program Counter (PC) ..................................................................................................... 75

Register 17: Program Status Register (PSR) ........................................................................................ 76

Register 18: Priority Mask Register (PRIMASK) .................................................................................... 80

Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 81

Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 82

Register 21: Control Register (CONTROL) ........................................................................................... 83

Cortex-M3 Peripherals ................................................................................................................. 108

Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 123

Register 5: Interrupt 32-54 Set Enable (EN1), offset 0x104 ................................................................ 124

Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 125

Register 7: Interrupt 32-54 Clear Enable (DIS1), offset 0x184 ............................................................ 126

Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 127

Register 9: Interrupt 32-54 Set Pending (PEND1), offset 0x204 ......................................................... 128

Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 129

Register 11: Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284 .................................................. 130

Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 131

Register 13: Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304 ........................................................... 132

Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 133

Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 133

Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 133

Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 133

Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 133

Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 133

Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 133

Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 133

Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 133

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Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 133

Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 133

Register 25: Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 133

Register 26: Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 133

Register 27: Interrupt 52-54 Priority (PRI13), offset 0x434 ................................................................... 133

Register 28: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 135

Register 29: Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 136

Register 30: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 138

Register 31: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 139

Register 32: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 142

Register 34: System Control (SYSCTRL), offset 0xD10 ....................................................................... 145

Register 35: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 147

Register 36: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 149

Register 37: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 150

Register 38: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 151

Register 40: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 156

Register 41: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 162

Register 43: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 164

Register 44: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 165

Register 45: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 166

System Control ............................................................................................................................ 186

Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 205

Register 3: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 208

Register 4: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 210

Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 212

Register 6: Reset Cause (RESC), offset 0x05C ................................................................................ 214

Register 7: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 216

Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 221

Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 224

Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 227

Register 15: Device Identification 1 (DID1), offset 0x004 ..................................................................... 233

19July 02, 2011

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Stellaris

LM3S5P36 Microcontroller

Register 16: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 235

Register 17: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 236

Register 18: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 238

Register 19: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 240

Register 20: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 243

Register 21: Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 244

Register 22: Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 246

Register 23: Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 247

Register 36: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 279

Register 37: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 281

Register 38: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 283

Hibernation Module ..................................................................................................................... 285

Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 296

Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 299

Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 300

Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 303

Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 305

Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 309

Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 310

Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 311

Internal Memory ........................................................................................................................... 312

Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 321

Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 322

Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 323

Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 327

Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 329

Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 330

Register 9: Flash Control (FCTL), offset 0x0F8 ................................................................................. 331

Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 332

Register 11: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 333

July 02, 201120

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