FPGA设计经典指南：国外权威教程

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《The Design Warrior's Guide to FPGAs》是一本备受推崇的国外FPGA设计经典教材，由Clive“Max”Maxfield撰写，由Newnes出版，隶属于Elsevier集团。这本书在全球范围内享有盛誉，不局限于特定的FPGA产品线，旨在提供广泛且深入的FPGA设计基础知识和技术指导。作者Maxfield凭借其丰富的经验和深厚的专业知识，使读者能够系统地理解和掌握FPGA设计的关键概念和技术。本书涵盖了FPGA的基本原理、设计流程、逻辑综合、布局布线、时序分析以及高级设计策略等内容。读者可以从中学习到如何利用FPGA实现定制化的硬件设计，包括数字信号处理、嵌入式系统、硬件加速等方面的应用。此外，书中还强调了设计实战技巧和最佳实践，使读者能够在实际项目中灵活运用所学知识。版权方面，该书受到Mentor Graphics Corporation和Xilinx, Inc.的共同许可，所有内容受到法律保护。未经事先书面许可，任何形式的复制、存储、传播或传递都必须得到出版商Elsevier的明确授权。想要获取权限的读者可以通过电话、传真或电子邮件联系英国牛津的Science & Technology Rights部门，或者在线访问Elsevier的网站通过"客户服务"并选择"获取权限"来申请。为了确保书籍内容的长期保存价值，Elsevier尽可能采用无酸纸印刷，体现了对学术知识传承的重视。在图书馆分类上，这本书也进行了相应的记录，便于查找和引用。《The Design Warrior's Guide to FPGAs》是一本极具实用价值的FPGA设计入门指南，不仅适合初学者系统学习，也是经验丰富的工程师进行技术提升和查阅参考资料的理想选择。它将帮助读者在快速变化的FPGA技术领域中保持竞争力，并在实际设计挑战中找到解决方案。

I would also like to mention the fact that the folks at 0-In,

AccelChip, Actel, Aldec, Altera, Altium, Axis, Cadence,

Carbon, Celoxica, Elanix, InTime, Magma, picoChip, Quick

Logic, QuickSilver, Synopsys, Synplicity, The MathWorks,

Hier Design, and Verisity were extremely helpful.

It also

behooves me to mention that Tom Hawkins from Launchbird

Design Systems went above and beyond the call of duty in

giving me his sagacious observations into open-source design

tools. Similarly, Dr. Eric Bogatin at GigaTest Labs was kind

enough to share his insights into signal integrity effects at the

circuit board level.

Last, but certainly not least, thanks go once again to my

publisher—Carol Lewis at Elsevier Science—for allowing me

to abstract the contents of appendix B from my book Designus

Maximus Unleashed (ISBN 0-7506-9089-5) and also for allow-

ing me to abstract the contents of appendix C from my book

Bebop to the Boolean Boogie (An Unconventional Guide to Elec-

tronics), Second Edition (ISBN 0-7506-7543-8).

xvi ■ The Design Warrior's Guide to FPGAs

1. If I’ve forgotten anyone, I’m really sorry (let me know, and I’ll add you

into the book for the next production run).

mable logic devices (PLDs), application-specific integrated circuits

(ASICs), application-specific standard parts (ASSPs), and—of

course—FPGAs.

For the purposes of this portion of our discussion, we shall

consider the term PLD to encompass both simple programmable

logic devices (SPLDs) and complex programmable logic devices

(CPLDs).

Various aspects of PLDs, ASICs, and ASSPs will be intro

duced in more detail in chapters 2 and 3. For the nonce, we

need only be aware that PLDs are devices whose internal

architecture is predetermined by the manufacturer, but which

are created in such a way that they can be configured (pro

grammed) by engineers in the field to perform a variety of

different functions. In comparison to an FPGA, however,

these devices contain a relatively limited number of logic

gates, and the functions they can be used to implement are

much smaller and simpler.

At the other end of the spectrum are ASICs and ASSPs,

which can contain hundreds of millions of logic gates and can

be used to create incredibly large and complex functions.

ASICs and ASSPs are based on the same design processes and

manufacturing technologies. Both are custom-designed to

address a specific application, the only difference being that

an ASIC is designed and built to order for use by a specific

company, while an ASSP is marketed to multiple customers.

(When we use the term ASIC henceforth, it may be assumed

that we are also referring to ASSPs unless otherwise noted or

where such interpretation is inconsistent with the context.)

Although ASICs offer the ultimate in size (number of

transistors), complexity, and performance; designing and

building one is an extremely time-consuming and expensive

process, with the added disadvantage that the final design is

“frozen in silicon” and cannot be modified without creating a

new version of the device.

Thus, FPGAs occupy a middle ground between PLDs and

ASICs because their functionality can be customized in the

2 ■ The Design Warrior's Guide to FPGAs

PLD is pronounced by

spelling it out as “P-L-D.”

SPLD is pronounced

by spelling it out as

“S-P-L-D.”

CPLD is pronounced

by spelling it out as

“C-P-L-D.”

ASIC is pronounced

“A-SIC.” That is, by spell

ing out the “A” to rhyme

with “hay,” followed by

“SIC” to rhyme with “tick.”

ASSP is pronounced

by spelling it out as

“A-S-S-P.”

field like PLDs, but they can contain millions of logic gates

and be used to implement extremely large and complex func

tions that previously could be realized only using ASICs.

The cost of an FPGA design is much lower than that of an

ASIC (although the ensuing ASIC components are much

cheaper in large production runs). At the same time, imple

menting design changes is much easier in FPGAs, and the

time-to-market for such designs is much faster. Thus, FPGAs

make a lot of small, innovative design companies viable

because—in addition to their use by large system design

houses—FPGAs facilitate “Fred-in-the-shed”–type operations.

This means they allow individual engineers or small groups of

engineers to realize their hardware and software concepts on

an FPGA-based test platform without having to incur the

enormous nonrecurring engineering (NRE) costs or purchase the

expensive toolsets associated with ASIC designs. Hence, there

were estimated to be only 1,500 to 4,000 ASIC design starts

and 5,000 ASSP design starts in 2003 (these numbers are fal-

ling dramatically year by year), as opposed to an educated

“guesstimate” of around 450,000 FPGA design starts

in the

same year.

Introduction ■ 3

NRE is pronounced by

spelling it out as “N-R-E.”

The concept of what actually comprises a “logic gate” becomes a little

murky in the context of FPGAs. This topic will be investigated in

excruciating detail in chapter 4.

This number is pretty vague because it depends on whom you talk to (not

surprisingly, FPGA vendors tend to proclaim the lowest possible estimate,

while other sources range all over the place).

Another reason these numbers are a little hard to pin down is that it’s

difficult to get everyone to agree what a “design start” actually is. In the

case of an ASIC, for example, should we include designs that are canceled

in the middle, or should we only consider designs that make it all the way

to tape-out? Things become even fluffier when it comes to FPGAs due to

their reconfigurability. Perhaps more telling is the fact that, after pointing

me toward an FPGA-centric industry analyst’s Web site, a representative

from one FPGA vendor added, “But the values given there aren’t very

accurate.” When I asked why, he replied with a sly grin, “Mainly because

we don’t provide him with very good data!”

What can FPGAs be used for?

When they first arrived on the scene in the mid-1980s,

FPGAs were largely used to implement glue logic,

medium-

complexity state machines, and relatively limited data proc

essing tasks. During the early 1990s, as the size and

sophistication of FPGAs started to increase, their big markets

at that time were in the telecommunications and networking

arenas, both of which involved processing large blocks of data

and pushing that data around. Later, toward the end of the

1990s, the use of FPGAs in consumer, automotive, and indus

trial applications underwent a humongous growth spurt.

FPGAs are often used to prototype ASIC designs or to

provide a hardware platform on which to verify the physical

implementation of new algorithms. However, their low devel-

opment cost and short time-to-market mean that they are

increasingly finding their way into final products (some of the

major FPGA vendors actually have devices that they specifi-

cally market as competing directly against ASICs).

By the early-2000s, high-performance FPGAs containing

millions of gates had become available. Some of these devices

feature embedded microprocessor cores, high-speed input/out-

put (I/O) interfaces, and the like. The end result is that

today’s FPGAs can be used to implement just about anything,

including communications devices and software-defined

radios; radar, image, and other digital signal processing (DSP)

applications; all the way up to system-on-chip (SoC)

compo

nents that contain both hardware and software elements.

4 ■ The Design Warrior's Guide to FPGAs

I/O is pronounced

by spelling it out as “I-O.”

SoC is pronounced by

spelling it out as “S-O-C.”

The term glue logic refers to the relatively small amounts of simple logic

that are used to connect (“glue”)—and interface between—larger logical

blocks, functions, or devices.

Although the term system-on-chip (SoC) would tend to imply an entire

electronic system on a single device, the current reality is that you

invariably require additional components. Thus, more accurate

appellations might be subsystem-on-chip (SSoC) or part of a system-on-chip

(PoaSoC).

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