STM32F4xxx Cortex-M4编程手册：处理器性能与微控制器应用

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"STM32F4xxx的CORTEX-M4内核编程手册" 这篇编程手册是针对STM32F4系列微控制器的，基于ARM Cortex-M4内核，旨在为应用级和系统级软件开发者提供详尽的编程指导。手册涵盖了STM32F4xx处理器的编程模型、指令集以及核心外设的完整描述。 STM32F4系列的Cortex-M4处理器是面向微控制器市场的高性能32位处理器，其主要特点包括： 1. 强大的处理性能与快速中断处理：处理器设计考虑了实时性，能在处理高负载任务的同时，迅速响应中断请求，适用于需要快速响应的实时应用。 2. 丰富的调试功能：通过广泛的断点和追踪能力，提升系统调试效率，使得开发者能更准确地定位和解决问题。 3. 高效的处理器核心、系统及内存结构：优化的架构设计确保了高效执行代码，并提供了高效的内存访问机制。 4. 超低功耗：集成的睡眠模式使得在不牺牲性能的情况下，能够显著降低功耗，适用于电池供电或对能耗敏感的设备。 5. 平台安全：处理器内置的安全特性，为应用程序和数据安全提供了保障。手册适用于表1中列出的产品和工具，包括STM32F4系列的微控制器以及相关的评估工具如STM32F4DISCOVERY开发板。开发者可以通过这些资源进行实际操作和测试。手册内容广泛，包含但不限于以下部分： 1. 关于文档：介绍了文档的使用和排版规则。 2. 类型和部件编号：列出了适用的微控制器型号和评估工具。 3. 编程模型：详细阐述了Cortex-M4处理器的体系结构和编程方式。 4. 指令集：全面解析了Cortex-M4支持的指令，包括数据处理、运算、分支、控制流等。 5. 核心外设：详细介绍了处理器内部的定时器、中断控制器、串行通信接口、GPIO、DMA等外设的使用方法。 6. 系统级特性：如电源管理、时钟系统、存储器配置等。 7. 应用示例和开发流程：提供了实际开发中的例子和步骤，帮助开发者理解和应用相关知识。 8. 错误处理和异常处理：讨论了程序错误和异常情况的处理策略。 9. 低功耗模式：详细解释了不同低功耗模式的设置和转换，以及如何在这些模式下保持系统运行。 10. 调试和追踪：介绍如何利用调试工具进行程序追踪和问题排查。这份编程手册是STM32F4系列开发者的重要参考资料，不仅涵盖了理论知识，还提供了实践指南，有助于开发者深入理解和有效利用Cortex-M4内核的全部潜力。

The Cortex-M4 processor PM0214

16/243 Doc ID 022708 Rev 2

2 The Cortex-M4 processor

2.1 Programmers model

This section describes the Cortex-M4 programmers model. In addition to the individual core

for software execution and stacks.

2.1.1 Processor mode and privilege levels for software execution

The processor modes are:

The privilege levels for software execution are:

2.1.2 Stacks

The processor uses a full descending stack. This means the stack pointer indicates the last

stacked item on the stack memory. When the processor pushes a new item onto the stack, it

decrements the stack pointer and then writes the item to the new memory location. The

processor implements two stacks, the main stack and the process stack, with independent

copies of the stack pointer, see Stack pointer on page 18.

In Thread mode, the CONTROL register controls whether the processor uses the main

stack or the process stack, see CONTROL register on page 24. In Handler mode, the

processor always uses the main stack. The options for processor operations are:

Thread mode: Used to execute application software.

The processor enters Thread mode when it comes out of reset.

The CONTROL register controls whether software execution is

privileged or unprivileged, see CONTROL register on page 24.

Handler mode: Used to handle exceptions.

The processor returns to Thread mode when it has finished exception

processing.

Software execution is always privileged.

Unprivileged: Unprivileged software executes at the unprivileged level and:

● Has limited access to the MSR and MRS instructions, and cannot

use the CPS instruction

● Cannot access the system timer, NVIC, or system control block

● Might have restricted access to memory or peripherals

● Must use the SVC instruction to make a supervisor call to transfer

control to privileged software

Privileged: Privileged software executes at the privileged level and can use all the

instructions and has access to all resources.

Can write to the CONTROL register to change the privilege level for

software execution.

The Cortex-M4 processor PM0214

18/243 Doc ID 022708 Rev 2

General-purpose registers

R0-R12 are 32-bit general-purpose registers for data operations.

Stack pointer

The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register

indicates the stack pointer to use:

● 0: Main Stack Pointer (MSP). This is the reset value.

● 1: Process Stack Pointer (PSP).

On reset, the processor loads the MSP with the value from address 0x00000000.

Link register

The Link Register (LR) is register R14. It stores the return information for subroutines,

function calls, and exceptions. On reset, the processor loads the LR value 0xFFFFFFFF.

Program counter

The Program Counter (PC) is register R15. It contains the current program address. On

reset, the processor loads the PC with the value of the reset vector, which is at address

0x00000004. Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1.

Program status register

The Program Status Register (PSR) combines:

● Application Program Status Register (APSR)

● Interrupt Program Status Register (IPSR)

● Execution Program Status Register (EPSR)

These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments are

as shown in Figure 3 and Figure 4.

ASPR read-write Either Unknown

Application program status register on

page 20

IPSR read-only Privileged 0x00000000

Interrupt program status register on

page 21

EPSR read-only Privileged 0x01000000

Execution program status register on

page 21

PRIMASK read-write Privileged 0x00000000 Priority mask register on page 23

FAULTMASK read-write Privileged 0x00000000 Fault mask register on page 23

BASEPRI read-write Privileged 0x00000000 Base priority mask register on page 24

CONTROL read-write Privileged 0x00000000 CONTROL register on page 24

1. Describes access type during program execution in thread mode and Handler mode. Debug access can

differ.

2. An entry of Either means privileged and unprivileged software can access the register.

Table 3. Core register set summary (continued)

Name Type

(1)

Required

privilege

(2)

Reset

value

Description

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