SystemVerilog验证方法手册：提升测试平台可重用性

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"vmm_sv.pdf 是一份关于SystemVerilog验证方法的手册，旨在指导如何使用VMM（Virtual Machine Model）构建测试平台，提高仿真复用性。该手册由Janick Bergeron、Eduard Cerny、Alan Hunter和Andrew Nightingale等人撰写，涵盖了Verilog硬件描述语言在集成电路验证中的应用。" SystemVerilog是一种强大的硬件描述语言，它扩展了传统的Verilog，增加了面向对象的编程特性，使得验证工作更加高效和结构化。VMM（Verification Methodology Manual for SystemVerilog）是基于SystemVerilog的一种验证方法论，它提供了一套框架和库，用于构建可复用的验证环境。在VMM中，重点在于模块化和组件化的测试平台设计。这包括验证组件（Verification Components）、类库（Class Libraries）以及验证机制（Verification Mechanisms）。验证组件是验证环境的基本构建块，它们可以被重用并组合在一起，以模拟待验证设计的行为。类库则包含了各种预定义的类，如随机化器（Randomizers）、覆盖驱动器（Cover Drivers）和监控器（Monitors），这些工具帮助开发者编写更有效的测试用例和验证覆盖。 VMM的关键概念包括： 1. **OOP（面向对象编程）**：利用SystemVerilog的类和继承，VMM允许创建可复用的验证类，增强了代码的组织性和可维护性。 2. **抽象层（Abstraction Layers）**：VMM通过不同的抽象层次，如接口层、事务层和原始数据层，简化了复杂设计的验证。 3. **环境（Environments）**：VMM的环境是验证的核心，它包含组件、激励源、监控器和覆盖点，用于全面验证设计的功能和性能。 4. **共享变量（Shared Variables）**：VMM利用SystemVerilog的共享变量实现组件间的通信，确保了在并发执行时的数据一致性。 5. **覆盖（Coverage）**：VMM提供了丰富的覆盖模型，帮助确保验证的完整性，确保测试用例能够充分探索设计空间。通过遵循VMM方法论，开发者可以创建高效、结构化且可扩展的验证环境，从而加速IC验证过程，降低出错风险，并提高整体的设计质量。这份手册是学习和应用VMM的重要参考资料，包含了丰富的实例和最佳实践，对于任何从事SystemVerilog验证工作的工程师来说都是宝贵的资源。

Preface

xvi Verification Methodology Manual for SystemVerilog

Chapter 4 describes the components of a verification environment and how to

implement them. Its companion Appendix A specifies a set of base and utility classes

that are used to implement the generic functionality required by all environments and

components.

Chapter 5 describes how to provide stimulus to the design under verification and how

it can be constrained to create interesting conditions. The generator classes specified

in Appendix A help to rapidly create VMM-compliant generator components.

Chapter 6 describes how to use qualitative metrics to drive the verification process

and using a constrainable random verification environment built using the guidelines

presented in the previous chapters to efficiently implement it.

Chapter 7 describes how assertions can be used with formal technology. Only a subset

of the checkers described in Appendix B can be used within this context.

Chapter 8 describes how the principles presented in the previous chapters can be

leveraged for system-level verification. Its companion Appendix C specifies a

command language and extensible component infrastructure to implement block and

system-level verification environments.

Chapter 9 describes how the integration of a general-purpose programmable

processor in a system can be verified using a set of predefined C functions described

in Appendix D.

The support infrastructure is specified in appendices A through D by describing the

interface and functionality of each element. No implementation is provided. It is up to

each vendor to provide a suitable implementation. This gives the opportunity to EDA

or IP vendors to optimize the implementation of the infrastructure for their particular

platform. It also eliminates the risk that unintended side effects of a particular

"reference" implementation might be interpreted as expected behavior. The code for

the interface specifications is available at the companion Web site:

http://vmm-sv.org

Note that the methodology can be followed without using the support elements

specified in the appendices. Any functionally equivalent set of elements, providing

similar functionality, would work. However, using a different set of support elements

will likely diminish the interoperability of verification components and environments

written using different support infrastructures.

How to Read this Book

Verification Methodology Manual for SystemVerilog xvii

HOW TO READ THIS BOOK

This book is not designed as a textbook that can be read and applied linearly.

Although the authors have made their best effort to present the material in a logical

order, it will be often difficult to appreciate the importance or wisdom of some

elements of the methodology without a grasp of the overall picture. Unfortunately, it

is not possible to draw an overall picture without first building the various elements

used to construct it.

The chicken-and-egg paradox is inherent to describing methodologies. A

methodology is about taking steps today to make life easier in some future. A

successful methodology will help reduce the overall cost of a project through

investments at earlier stages that will provide greater returns later on. In a practical

description of a methodology, it is difficult to justify some of the initial costs as their

future benefit is not immediately apparent. Similarly, describing the future benefits is

not possible without describing the elements that, when put together, will create these

benefits.

A reader unfamiliar with an equivalent methodology would typically require two

readings of the entire book. A first reading will help form the overall picture of the

methodology, how the various elements fit together and the benefits that can be

realized. A second reading will help appreciate its detailed implementation process

and supporting library.

Although everyone will benefit from reading the entire book, there are sections that

are more relevant to specific verification tasks. Designers must read Chapter 3. They

should also read Chapter 7 if they intend to use formal technology to verify their

design. Verification leaders and project managers should read Chapters 2 and 6.

Verification engineers responsible for the implementation and maintenance of the

verification environment must read Chapters 4 and 5 and should read Chapter 8.

Verification IP developers should read Chapters 4 and 8. Verification engineers

responsible for implementing testcases should read the first half of Chapter 5. If they

are also responsible for implementing functional coverage points, they should read

the second half of Chapter 6. Embedded software verification engineers should read

Chapter 9.

Preface

xviii Verification Methodology Manual for SystemVerilog

FOR MORE INFORMATION

At the time of writing, SystemVerilog was in the process of being ratified as an IEEE

standard. In addition to several books already—or to be—published, more

information about SystemVerilog can be obtained from:

http://www.eda.org/sv

http://www.eda.org/sv-ieee1800

This book assumes the reader has experience with the entire SystemVerilog language.

It is not designed as an introductory or training text to the verification or assertion

constructs. The following books, listed in alphabetical order, can be used to gain the

necessary experience and knowledge of the language constructs:

Janick Bergeron, "Writing Testbenches Using SystemVerilog", Springer

Ben Cohen, Srinivasan Venkataramanan and Ajeetha Kumari, "SystemVerilog

Assertions Handbook", VhdlCohen Publishing

Chris Spear and Arturo Salz, "SystemVerilog for Verification", Springer

In this book, code examples are provided as extracts that focus on the various points

they are designed to illustrate. It does not contain a full example of the methodology

application within its page. Such an example would consume several tens of pages

filled with SystemVerilog code. It would be difficult to navigate, would become

obsolete as improvements to the methodology are made and impossible to actually

simulate. Pointers to several complete examples and the complete code that includes

the various examples can be found at the companion Web site:

http://vmm-sv.org

The companion Web site will also contain an errata for the latest edition of the book.

It may also publish additional guidelines as the methodology evolves and is

expanded. These additional guidelines will be included in future editions. Discussions

on the use or interpretation of the methodology and suggestions for improvement are

carried in the forums at:

http://verificationguild.com

ACKNOWLEDGEMENTS

The authors would like to thank Holger Keding for his contribution to Chapter 8.

They are also grateful for the thoughtful reviews and challenging comments from

Pierre Aulagnier, Oliver Bell, Michael Benjamin, Jonathan Bradford, Craig Deaton,

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