library ieee;
--use ieee.std_logic.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Library lpm;
use lpm.lpm_components.all;
Library Altera;
use Altera.Maxplus2.all;
entity nh035dn06 is
port(
clock : in std_logic;
---------------------------------------------------------------------
cp : inout std_logic;
de : inout std_logic;
hs : buffer std_logic;
vs : buffer std_logic;
disp_da : inout std_logic_vector(7 downto 0);
----------------------------------------------------------------------
-- ram_cs : out std_logic;
ram_wr : inout std_logic;
ram_addr : buffer std_logic_vector(17 downto 0);
ram_udqm : buffer std_logic;
ram_ldqm : buffer std_logic;
ram_data : inout std_logic_vector(7 downto 0);
----------------------------------------------------------------------
data : inout std_logic_vector(7 downto 0);
data_addr : in std_logic_vector(18 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
-- data_cs : in std_logic;
-- pin_busy : out std_logic;
lamp1 : out std_logic
);
end nh035dn06;
architecture en of nh035dn06 is
COMPONENT TFF
PORT ( t : IN STD_LOGIC;
clk : IN STD_LOGIC;
clrn: IN STD_LOGIC;
prn : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT DFF
PORT ( d : IN STD_LOGIC;
clk : IN STD_LOGIC;
clrn: IN STD_LOGIC;
prn : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END COMPONENT;
signal clock_times : std_logic_vector(1 downto 0);
signal clr_hs : std_logic;
signal data_addr1 : std_logic_vector(18 downto 0);
signal disp_addr : std_logic_vector(16 downto 0);
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