![](https://csdnimg.cn/release/download_crawler_static/10794854/bg12.jpg)
18 MIPS32® 74K™ Processor Core Family Software User’s Manual, Revision 01.05
Table 5.7: TLB Tag Entry Fields ............................................................................................................................. 98
Table 5.8: TLB Data Entry Fields............................................................................................................................ 98
Table 5.9: Machine Check Exception ................................................................................................................... 102
Table 5.10: TLB Instructions ................................................................................................................................. 103
Table 5.11: Cache Coherency Attributes .............................................................................................................. 104
Table 5.12: Cacheability of Segments with Fixed Mapping Translation................................................................ 104
Table 6.1: Priority of Exceptions ........................................................................................................................... 108
Table 6.2: Interrupt Modes.................................................................................................................................... 110
Table 6.3: Relative Interrupt Priority for Vectored Interrupt Mode......................................................................... 113
Table 6.4: Exception Vector Offsets for Vectored Interrupts................................................................................. 118
Table 6.5: Exception Vector Base Addresses, SI_UseExceptionBase = 0........................................................... 120
Table 6.6: Exception Vector Base Addresses, SI_UseExceptionBase = 1........................................................... 120
Table 6.8: Exception Vectors ................................................................................................................................ 121
Table 6.7: Exception Vector Offsets ..................................................................................................................... 121
Table 6.9: Value Stored in EPC, ErrorEPC, or DEPC on Exception..................................................................... 123
Table 6.10: Debug Exception Vector Addresses .................................................................................................. 126
Table 6.11: DebugVectorAddr Register Field Descriptions................................................................................... 126
Table 6.12: Register States an Interrupt Exception .............................................................................................. 130
Table 6.13: Register States on Watch Exception.................................................................................................. 131
Table 6.14: CP0 Register States on Address Exception Error.............................................................................. 132
Table 6.15: CP0 Register States on TLB Refill Exception .................................................................................... 132
Table 6.16: CP0 Register States on TLB Invalid Exception.................................................................................. 133
Table 6.17: CP0 Register States on Cache Error Exception ................................................................................ 133
Table 6.18: Register States on Coprocessor Unusable Exception ....................................................................... 135
Table 6.19: Register States on Floating Point Exception...................................................................................... 136
Table 6.20: Register States on TLB Modified Exception....................................................................................... 138
Table 7.1: CP0 Registers in Alphabetical Order ................................................................................................... 145
Table 7.2: CP0 Registers in Numerical Order....................................................................................................... 146
Table 7.3: CP0 Registers Grouped by Function ................................................................................................... 149
Table 7.4: CP0 Register Field R/W Access Types................................................................................................ 150
Table 7.6: Field Descriptions for Random Register .............................................................................................. 152
Table 7.5: Field Descriptions for Index Register ................................................................................................... 152
Table 7.7: Field Descriptions for EntryLo0-1 Register .......................................................................................... 153
Table 7.8: Cache Coherency Attributes encoding of C field of EntryLo0-1 and K0 field of Config Register......... 153
Table 7.9: Context Register Field Descriptions.................................................................................................... 154
Table 7.11: Recommended ContextConfig Values............................................................................................... 156
Table 7.12: UserLocal Register Field Description................................................................................................. 156
Table 7.10: ContextConfig Register Field Descriptions ....................................................................................... 156
Table 7.13: Field Descriptions for PageMask Register......................................................................................... 157
Table 7.14: Field Descriptions for Wired Register................................................................................................. 158
Table 7.15: Field Descriptions for HWREna Register........................................................................................... 159
Table 7.16: BadVAddr Register Field Description................................................................................................. 160
Table 7.17: Count Register Field Description ....................................................................................................... 161
Table 7.18: Field Descriptions for EntryHi Register .............................................................................................. 161
Table 7.19: Compare Register Field Description .................................................................................................. 162
Table 7.20: Field Descriptions for Status Register................................................................................................ 164
Table 7.21: Field Descriptions for IntCtl Register.................................................................................................. 168
Table 7.22: Field Descriptions for SRSCtl Register .............................................................................................. 170
Table 7.23: Sources for SRSCtl
CSS
on an Exception or Interrupt......................................................................... 171
Table 7.24: Field Descriptions for SRSMap Register............................................................................................ 172
Table 7.25: Field Descriptions for Cause Register................................................................................................ 173
Table 7.26: Exception Code values in ExcCode Field of Cause Register ............................................................ 175
Table 7.27: EPC Register Field Description.......................................................................................................... 177