MIPS32® 74K™处理器核心系列软件用户手册简介

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MIPS32® 74KTM 处理器核心家族软件用户手册本手册介绍了 MIPS32 74KTM 处理器核心家族的软件使用手册，涵盖了处理器核心的架构、指令集、内存管理、缓存、_scratchpad 内存、接口、电源控制、调试等方面的知识点。一、处理器核心架构 MIPS32 74KTM 处理器核心家族基于 MIPS32 架构，采用流水线式设计，具有高性能和低功耗的特点。处理器核心架构包括指令获取单元（IFU）、指令缓存、指令解码/派遣单元（IDU）、指令执行单元（IEU）、乘除单元（MDU）、CorExtend 用户定义指令（UDI）、加载存储单元（LSU）、系统控制协处理器（CP0）、内存管理单元（MMU）、数据缓存、_scratchpad RAM、毕业单元（GRU）、总线接口单元（BIU）和 coprocessor 接口单元（CIU）。二、指令集 MIPS32 74KTM 处理器核心家族支持 MIPS32 指令集，包括整数指令、浮点数指令、加载存储指令、跳转指令等。CorExtend 用户定义指令（UDI）允许用户自定义指令，以满足特定的应用需求。三、内存管理和缓存 MIPS32 74KTM 处理器核心家族具有内存管理单元（MMU），支持虚拟内存和分页机制。数据缓存和指令缓存可以提高处理器的执行速度。Scratchpad 内存是一种快速的内部存储器，用于存储应用程序的关键数据。四、接口和电源控制 MIPS32 74KTM 处理器核心家族具有多种接口，包括总线接口单元（BIU）和 coprocessor 接口单元（CIU）。电源控制单元可以动态地控制处理器的电源消耗，以减少功耗。五、调试和其他 MIPS32 74KTM 处理器核心家族支持 EJTAG 调试接口，允许开发者对处理器进行调试和测试。Graduation Unit (GRU) 是一个特殊的单元，用于处理器的毕业和初始化。 MIPS32 74KTM 处理器核心家族软件用户手册提供了处理器核心架构、指令集、内存管理、缓存、接口、电源控制、调试等方面的详细信息，为开发者提供了全面和详细的参考指南。

16 MIPS32® 74K™ Processor Core Family Software User’s Manual, Revision 01.05

Figure 7.57: DTagHi Register Format................................................................................................................... 218

Figure 7.58: L23DataHi Register Format .............................................................................................................. 218

Figure 7.59: ErrorEPC Register Format................................................................................................................ 219

Figure 7.60: DeSave Register Format .................................................................................................................. 219

Figure 9.1: Instruction Cache Organization .......................................................................................................... 226

Figure 9.2: Data Cache Organization ................................................................................................................... 228

Figure 11.1: Debug Control Register Format........................................................................................................ 240

Figure 11.2: IBS Register Format ......................................................................................................................... 250

Figure 11.3: IBAn Register Format ....................................................................................................................... 251

Figure 11.4: IBMn Register Format....................................................................................................................... 252

Figure 11.5: IBASIDn Register Format ................................................................................................................. 252

Figure 11.6: IBCn Register Format ....................................................................................................................... 253

Figure 11.7: DBS Register Format ....................................................................................................................... 254

Figure 11.8: DBAn Register Format ..................................................................................................................... 255

Figure 11.9: DBMn Register Format .................................................................................................................... 255

Figure 11.10: DBASIDn Register Format ............................................................................................................. 256

Figure 11.11: DBCn Register Format ................................................................................................................... 256

Figure 11.12: DBVn Register Format ................................................................................................................... 258

Figure 11.13: DBVHn Register Format ................................................................................................................ 258

Figure 11.14: TAP Controller State Diagram ........................................................................................................ 261

Figure 11.15: Concatenation of the EJTAG Address, Data and Control Registers............................................... 265

Figure 11.16: TDI to TDO Path When in Shift-DR State and FASTDATA Instruction is Selected........................ 265

Figure 11.17: Device Identification Register Format ............................................................................................ 267

Figure 11.18: Implementation Register Format .................................................................................................... 268

Figure 11.19: EJTAG Control Register Format .................................................................................................... 270

Figure 11.20: Endian Formats for PAD Register................................................................................................... 276

Figure 11.21: Fastdata Register Format .............................................................................................................. 276

Figure 11.22: TAP Register PCsample Format..................................................................................................... 279

Figure 11.23: Fast Debug Channel Buffer Organization....................................................................................... 282

Figure 11.24: FDC TAP Register Format.............................................................................................................. 283

Figure 11.25: FDC Access Control and Status Register Format .......................................................................... 284

Figure 11.26: FDC Configuration Register Format ............................................................................................... 285

Figure 11.27: FDC Status Register Format........................................................................................................... 286

Figure 11.28: FDC Receive Register Format........................................................................................................ 287

Figure 11.29: FDC Transmit Register Format....................................................................................................... 287

Figure 11.30: MIPS® Trace Functional Blocks in the 74K™ Core ...................................................................... 289

Figure 11.31: A TMOAS Trace Record................................................................................................................. 296

Figure 11.32: TCBCONTROLA Register Format ................................................................................................. 301

Figure 11.33: TCBCONTROLB Register Format ................................................................................................. 304

Figure 11.34: TCBDATA Register Format ........................................................................................................... 308

Figure 11.35: TCBCONTROLC Register Format ................................................................................................. 309

Figure 11.36: TCBCONTROLE Register Format ................................................................................................. 310

Figure 11.37: TCBCONFIG Register Format ....................................................................................................... 311

Figure 11.38: TCBTW Register Format ............................................................................................................... 313

Figure 11.39: TCBRDP Register Format ............................................................................................................. 313

Figure 11.40: TCBWRP Register Format ............................................................................................................. 314

Figure 11.41: TCBSTP Register Format .............................................................................................................. 314

Figure 11.42: TCBTRIGx Register Format ........................................................................................................... 315

Figure 11.43: TCB Trigger Processing Overview.................................................................................................. 321

Figure 12.1: Instruction Formats .......................................................................................................................... 328

Figure 13.1: Usage of Address Fields to Select Index and Way........................................................................... 347

MIPS32® 74K™ Processor Core Family Software User’s Manual, Revision 01.05 17

List of Tables

Table 2.1: 74K™ Core Pipeline Stages Descriptions.............................................................................................. 38

Table 2.2: Execution Hazards................................................................................................................................. 46

Table 2.3: Instruction Hazards ................................................................................................................................ 47

Table 2.4: Hazard Instruction Listing ...................................................................................................................... 47

Table 3.1: Parameters of Floating-Point Data Types.............................................................................................. 51

Table 3.2: Value of Single or Double Floating-Point Data Type Encoding.............................................................. 52

Table 3.3: Value Supplied When a New Quiet NaN is Created .............................................................................. 54

Table 3.4: Coprocessor 1 Register Summary......................................................................................................... 58

Table 3.5: Read/Write Properties............................................................................................................................ 58

Table 3.6: FIR Bit Field Descriptions....................................................................................................................... 59

Table 3.7: FCCR Bit Field Descriptions .................................................................................................................. 60

Table 3.8: FEXR Bit Field Descriptions................................................................................................................... 61

Table 3.9: FENR Bit Field Descriptions................................................................................................................... 61

Table 3.10: FCSR Bit Field Descriptions................................................................................................................. 62

Table 3.11: Cause, Enables, and Flags Definitions ................................................................................................ 63

Table 3.12: Rounding Mode Definitions.................................................................................................................. 64

Table 3.13: Handling Denormalized Floating-point Numbers ................................................................................. 64

Table 3.14: Zero Flushing for Tiny Results ............................................................................................................. 65

Table 3.15: Handling of Denormalized Operand Values and Tiny Results Based on FS Bit Setting...................... 65

Table 3.16: Handling of Tiny Intermediate Result Based on the FO and FS Bit Settings....................................... 65

Table 3.17: Handling of Tiny Final Result Based on FN and FS Bit Settings ......................................................... 66

Table 3.18: Recommended FS/FO/FN Settings ..................................................................................................... 67

Table 3.19: FPU Data Transfer Instructions............................................................................................................ 69

Table 3.20: FPU Loads and Stores Using Register+Offset Address Mode ............................................................ 69

Table 3.21: FPU Loads and Stores Using Register+Register Address Mode ........................................................ 69

Table 3.22: FPU Move To and From Instructions ................................................................................................... 69

Table 3.23: FPU IEEE Arithmetic Operations ......................................................................................................... 70

Table 3.24: FPU-Approximate Arithmetic Operations............................................................................................. 70

Table 3.25: FPU Multiply-Accumulate Arithmetic Operations ................................................................................. 71

Table 3.26: FPU Conversion Operations Using the FCSR Rounding Mode........................................................... 71

Table 3.27: FPU Conversion Operations Using a Directed Rounding Mode .......................................................... 71

Table 3.28: FPU Formatted Operand Move Instruction .......................................................................................... 72

Table 3.29: FPU Conditional Move on True/False Instructions............................................................................... 72

Table 3.30: FPU Conditional Move on Zero/Non-Zero Instructions ........................................................................ 72

Table 3.31: FPU Conditional Branch Instructions ................................................................................................... 73

Table 3.32: Deprecated FPU Conditional Branch Likely Instructions ..................................................................... 73

Table 3.33: CPU Conditional Move on FPU True/False Instructions...................................................................... 73

Table 3.34: Result for Exceptions Not Trapped ...................................................................................................... 74

Table 3.35: 74Kf Core FPU Latency and Repeat Rate........................................................................................... 79

Table 4.1: MIPS® DSP ASE Control Register (DSPControl) Field Descriptions .................................................... 82

Table 4.2: DSPControl ouflag Bits ......................................................................................................................... 83

Table 5.1: User Mode Segments ............................................................................................................................ 90

Table 5.2: Supervisor Mode Segments................................................................................................................... 92

Table 5.3: Kernel Mode Segments ......................................................................................................................... 94

Table 5.4: Physical Address and Cache Attributes for dseg, dmseg, and drseg .................................................... 96

Table 5.5: CPU Access to drseg............................................................................................................................. 96

Table 5.6: CPU Access to dmseg ........................................................................................................................... 96

18 MIPS32® 74K™ Processor Core Family Software User’s Manual, Revision 01.05

Table 5.7: TLB Tag Entry Fields ............................................................................................................................. 98

Table 5.8: TLB Data Entry Fields............................................................................................................................ 98

Table 5.9: Machine Check Exception ................................................................................................................... 102

Table 5.10: TLB Instructions ................................................................................................................................. 103

Table 5.11: Cache Coherency Attributes .............................................................................................................. 104

Table 5.12: Cacheability of Segments with Fixed Mapping Translation................................................................ 104

Table 6.1: Priority of Exceptions ........................................................................................................................... 108

Table 6.2: Interrupt Modes.................................................................................................................................... 110

Table 6.3: Relative Interrupt Priority for Vectored Interrupt Mode......................................................................... 113

Table 6.4: Exception Vector Offsets for Vectored Interrupts................................................................................. 118

Table 6.5: Exception Vector Base Addresses, SI_UseExceptionBase = 0........................................................... 120

Table 6.6: Exception Vector Base Addresses, SI_UseExceptionBase = 1........................................................... 120

Table 6.8: Exception Vectors ................................................................................................................................ 121

Table 6.7: Exception Vector Offsets ..................................................................................................................... 121

Table 6.9: Value Stored in EPC, ErrorEPC, or DEPC on Exception..................................................................... 123

Table 6.10: Debug Exception Vector Addresses .................................................................................................. 126

Table 6.11: DebugVectorAddr Register Field Descriptions................................................................................... 126

Table 6.12: Register States an Interrupt Exception .............................................................................................. 130

Table 6.13: Register States on Watch Exception.................................................................................................. 131

Table 6.14: CP0 Register States on Address Exception Error.............................................................................. 132

Table 6.15: CP0 Register States on TLB Refill Exception .................................................................................... 132

Table 6.16: CP0 Register States on TLB Invalid Exception.................................................................................. 133

Table 6.17: CP0 Register States on Cache Error Exception ................................................................................ 133

Table 6.18: Register States on Coprocessor Unusable Exception ....................................................................... 135

Table 6.19: Register States on Floating Point Exception...................................................................................... 136

Table 6.20: Register States on TLB Modified Exception....................................................................................... 138

Table 7.1: CP0 Registers in Alphabetical Order ................................................................................................... 145

Table 7.2: CP0 Registers in Numerical Order....................................................................................................... 146

Table 7.3: CP0 Registers Grouped by Function ................................................................................................... 149

Table 7.4: CP0 Register Field R/W Access Types................................................................................................ 150

Table 7.6: Field Descriptions for Random Register .............................................................................................. 152

Table 7.5: Field Descriptions for Index Register ................................................................................................... 152

Table 7.7: Field Descriptions for EntryLo0-1 Register .......................................................................................... 153

Table 7.8: Cache Coherency Attributes encoding of C field of EntryLo0-1 and K0 field of Config Register......... 153

Table 7.9: Context Register Field Descriptions.................................................................................................... 154

Table 7.11: Recommended ContextConfig Values............................................................................................... 156

Table 7.12: UserLocal Register Field Description................................................................................................. 156

Table 7.10: ContextConfig Register Field Descriptions ....................................................................................... 156

Table 7.13: Field Descriptions for PageMask Register......................................................................................... 157

Table 7.14: Field Descriptions for Wired Register................................................................................................. 158

Table 7.15: Field Descriptions for HWREna Register........................................................................................... 159

Table 7.16: BadVAddr Register Field Description................................................................................................. 160

Table 7.17: Count Register Field Description ....................................................................................................... 161

Table 7.18: Field Descriptions for EntryHi Register .............................................................................................. 161

Table 7.19: Compare Register Field Description .................................................................................................. 162

Table 7.20: Field Descriptions for Status Register................................................................................................ 164

Table 7.21: Field Descriptions for IntCtl Register.................................................................................................. 168

Table 7.22: Field Descriptions for SRSCtl Register .............................................................................................. 170

Table 7.23: Sources for SRSCtl

CSS

on an Exception or Interrupt......................................................................... 171

Table 7.24: Field Descriptions for SRSMap Register............................................................................................ 172

Table 7.25: Field Descriptions for Cause Register................................................................................................ 173

Table 7.26: Exception Code values in ExcCode Field of Cause Register ............................................................ 175

Table 7.27: EPC Register Field Description.......................................................................................................... 177

MIPS32® 74K™ Processor Core Family Software User’s Manual, Revision 01.05 19

Table 7.28: Field Descriptions for PRId Register.................................................................................................. 177

Table 7.29: Field Descriptions for EBase Register ............................................................................................... 178

Table 7.30: CDMMBase Register Field Descriptions............................................................................................ 179

Table 7.31: Field Descriptions for Config Register................................................................................................ 180

Table 7.32: Field Descriptions for Config1 Register.............................................................................................. 182

Table 7.33: Field Descriptions for Config2 Register.............................................................................................. 183

Table 7.34: Field Descriptions for Config3 Register.............................................................................................. 184

Table 7.35: Field Descriptions for Config6 Register.............................................................................................. 185

Table 7.36: Field Descriptions for Config7 Register.............................................................................................. 187

Table 7.37: Field Descriptions for WatchLo0-3 Register....................................................................................... 190

Table 7.38: Field Descriptions for WatchHi0-3 Register ....................................................................................... 191

Table 7.39: Field Descriptions for Debug Register ............................................................................................... 192

Table 7.40: TraceControl Register Field Descriptions .......................................................................................... 195

Table 7.41: TraceControl2 Register Field Descriptions ........................................................................................ 198

Table 7.42: UserTraceData1 / UserTraceData2 Register Field Descriptions ....................................................... 200

Table 7.43: TraceIBPC Register Field Descriptions.............................................................................................. 200

Table 7.44: TraceDBPC Register Field Descriptions............................................................................................ 201

Table 7.45: BreakPoint Control Modes: IBPC and DBPC..................................................................................... 202

Table 7.46: DEPC Register Formats..................................................................................................................... 202

Table 7.47: TraceControl3 Register Field Descriptions ........................................................................................ 203

Table 7.48: Field Descriptions for PerfCtl0-3 Register.......................................................................................... 204

Table 7.49: Performance Counter Events and Codes .......................................................................................... 204

Table 7.50: Performance Counter Count Register Field Descriptions .................................................................. 209

Table 7.51: Field Descriptions for ErrCtl Register................................................................................................. 209

Table 7.52: Field Descriptions for CacheErr Register........................................................................................... 210

Table 7.53: Field Descriptions for ITagLo Register............................................................................................... 212

Table 7.55: Field Descriptions for ITagLo-SPR Register ...................................................................................... 213

Table 7.56: IDataLo Register Field Description .................................................................................................... 213

Table 7.54: Field Descriptions for ITagLo-WST Register...................................................................................... 213

Table 7.57: Field Descriptions for DTagLo Register ............................................................................................. 214

Table 7.58: Field Descriptions for DTagLo-WST Register.................................................................................... 215

Table 7.59: Field Descriptions for DTagLo-DYT Register..................................................................................... 215

Table 7.60: Field Descriptions for DTagLo-SPT Register..................................................................................... 216

Table 7.61: DDataLo Register Field Description................................................................................................... 216

Table 7.62: L23DataLo Register Field Description ............................................................................................... 217

Table 7.63: Field Descriptions for ITagHi Register ............................................................................................... 217

Table 7.65: Field Descriptions for DTagHi Register.............................................................................................. 218

Table 7.66: L23DataHi Register Field Description................................................................................................ 218

Table 7.64: IDataHi Register Field Description..................................................................................................... 218

Table 7.67: ErrorEPC Register Field Description.................................................................................................. 219

Table 7.68: DeSave Register Field Description .................................................................................................... 219

Table 9.1: Instruction Cache Attributes................................................................................................................. 225

Table 9.2: Data Cache Attributes.......................................................................................................................... 227

Table 9.3: Potential Virtual Aliasing Bits ............................................................................................................... 228

Table 9.4: Way Selection Encoding, 4 Ways ........................................................................................................ 233

Table 11.1: Debug Control Register Field Descriptions........................................................................................ 240

Table 11.2: Overview of Status Register for Instruction Breakpoints.................................................................... 245

Table 11.3: Overview of Registers for Each Instruction Breakpoint...................................................................... 245

Table 11.4: Overview of Status Register for Data Breakpoints............................................................................. 245

Table 11.5: Overview of Registers for Each Data Breakpoint............................................................................... 246

Table 11.6: Rules for Update of BS Bits on Data Breakpoint Exceptions............................................................. 249

Table 11.7: Addresses for Instruction Breakpoint Registers................................................................................. 250

Table 11.8: IBS Register Field Descriptions ......................................................................................................... 251

20 MIPS32® 74K™ Processor Core Family Software User’s Manual, Revision 01.05

Table 11.9: IBAn Register Field Descriptions ....................................................................................................... 251

Table 11.10: IBMn Register Field Descriptions..................................................................................................... 252

Table 11.11: IBASIDn Register Field Descriptions ............................................................................................... 252

Table 11.12: BCn Register Field Descriptions ...................................................................................................... 253

Table 11.13: Addresses for Data Breakpoint Registers........................................................................................ 254

Table 11.14: DBS Register Field Descriptions...................................................................................................... 254

Table 11.15: DBAn Register Field Descriptions.................................................................................................... 255

Table 11.16: DBMn Register Field Descriptions ................................................................................................... 255

Table 11.17: DBASIDn Register Field Descriptions.............................................................................................. 256

Table 11.18: DBCn Register Field Descriptions.................................................................................................... 256

Table 11.19: DBVn Register Field Descriptions.................................................................................................... 258

Table 11.21: EJTAG Interface Pins ...................................................................................................................... 259

Table 11.20: DBVHn Register Field Descriptions ................................................................................................. 259

Table 11.22: Implemented EJTAG Instructions .................................................................................................... 263

Table 11.24: Implementation Register Descriptions ............................................................................................. 268

Table 11.23: Device Identification Register Field Descriptions............................................................................. 268

Table 11.25: EJTAG Control Register Descriptions.............................................................................................. 270

Table 11.26: Fastdata Register Field Description................................................................................................. 276

Table 11.27: Operation of the FASTDATA Access............................................................................................... 277

Table 11.28: FDC TAP Register Field Descriptions.............................................................................................. 283

Table 11.29: FDC Register Mapping..................................................................................................................... 284

Table 11.30: FDC Access Control and Status Register Field Descriptions .......................................................... 284

Table 11.31: FDC Configuration Register Field Descriptions ............................................................................... 285

Table 11.32: FDC Status Register Field Descriptions........................................................................................... 286

Table 11.33: FDC Receive Register Field Descriptions........................................................................................ 287

Table 11.35: FDTXn Address Decode .................................................................................................................. 288

Table 11.34: FDC Transmit Register Field Descriptions....................................................................................... 288

Table 11.36: TMOAS Trace Record Field Descriptions....................................................................................... 296

Table 11.37: Mapping TCB Registers in drseg .................................................................................................... 298

Table 11.38: A List of Coprocessor 0 Trace Registers ......................................................................................... 300

Table 11.39: TCB EJTAG Registers ..................................................................................................................... 300

Table 11.40: Registers Selected by TCBCONTROLB.......................................................................................... 301

Table 11.41: TCBCONTROLA Register Field Descriptions.................................................................................. 302

Table 11.42: TCBCONTROLB Register Field Descriptions.................................................................................. 305

Table 11.43: Clock Ratio encoding of the CR field ............................................................................................... 308

Table 11.45: TCBCONTROLC Register Field Descriptions.................................................................................. 309

Table 11.44: TCBDATA Register Field Descriptions ............................................................................................ 309

Table 11.46: TCBCONTROLE Register Field Descriptions.................................................................................. 310

Table 11.47: TCBCONFIG Register Field Descriptions........................................................................................ 311

Table 11.48: TCBTW Register Field Descriptions ................................................................................................ 313

Table 11.49: TCBRDP Register Field Descriptions .............................................................................................. 313

Table 11.50: TCBWRP Register Field Descriptions.............................................................................................. 314

Table 11.51: TCBSTP Register Field Descriptions............................................................................................... 314

Table 11.52: TCBTRIGx Register Field Descriptions............................................................................................ 315

Table 12.1: Byte Access Within a Doubleword ..................................................................................................... 329

Table 13.1: Symbols Used in the Instruction Encoding Tables............................................................................. 333

Table 13.2: MIPS32 Encoding of the Opcode Field.............................................................................................. 334

Table 13.3: MIPS32 SPECIAL Opcode Encoding of Function Field..................................................................... 334

Table 13.4: MIPS32 REGIMM Encoding of rt Field............................................................................................... 334

Table 13.5: MIPS32 SPECIAL2 Encoding of Function Field................................................................................. 335

Table 13.6: MIPS32 Special3 Encoding of Function Field for Release 2 of the Architecture ............................... 335

Table 13.7: MIPS32 MOVCI Encoding of tf Bit ..................................................................................................... 335

Table 13.8: MIPS32 SRL Encoding of Shift/Rotate .............................................................................................. 335

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