MIPS32® 24K® Core家族编程指南：官方修订版

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编程MIPS32® 24K® 核心家族手册(MD00355, Revision 04.63, 发布日期：2008年12月19日)是MIPS Technologies, Inc.官方发布的文档，它提供了深入的指导，帮助开发人员理解和操作这款基于MIPS架构的24K系列处理器。这份手册详细涵盖了MIPS32指令集、硬件特性、寄存器使用、流水线操作以及内存管理等核心概念。该手册的重要知识点包括： 1. **MIPS32架构介绍**：MIPS32是MIPS技术公司针对32位应用设计的微处理器架构，24K系列是其中的一员，强调了其高性能、低功耗和灵活性。 2. **指令集详解**：手册详细列出了MIPS32指令集，包括基础运算指令、控制转移指令、数据处理指令和系统调用指令，帮助开发者编写高效的程序代码。 3. **寄存器使用**：24K核心提供了多个通用寄存器组，如累加器（$t0-$t7, $s0-$s7）和程序计数器（$pc），开发者需理解如何有效地管理和利用这些寄存器来优化程序性能。 4. **流水线设计**：手册解释了24K核心的流水线结构，这对于理解和避免潜在的性能瓶颈，如数据 hazards（数据相关和控制相关）至关重要。 5. **内存管理**：涵盖了内存寻址方式（如I/O映射、存储器分段）、缓存体系和内存访问权限控制，确保程序能够高效地访问和管理内存空间。 6. **中断处理和异常处理**：介绍了中断向量表、异常处理程序以及异常模式的使用，这对于处理突发情况和保证系统的健壮性非常重要。 7. **硬件验证与版权声明**：强调了版权保护，任何未经许可的复制、修改或使用MIPS32 24K核心相关资料的行为都将受到法律追究，提醒读者遵守知识产权法规。 8. **源格式文档**：手册以可修改的格式提供，如FrameMaker或MicroPress格式，便于用户进行学习和调试工作。这份手册对于想要开发MIPS32 24K平台应用的工程师来说，是一份不可或缺的参考资料，通过深入阅读和实践，可以掌握在该处理器上进行高效编程的技巧和最佳实践。

1.6 A brief guide to the 24K® core implementation

Programming the MIPS32® 24K® Core Family, Revision 04.63 16

Chapter 2

Programming the MIPS32® 24K® Core Family, Revision 04.63 17

Initialization and identity

What happens when the CPU is ﬁrst powered up? These functions are perhaps more often associated with a ROM

monitor than an OS.

2.1 Probing your CPU - Conﬁg CP0 registers

The four registers Conﬁg and Conﬁg1-3 are 32-bit CP0 registers which contain information about the CPU’s capa-

bilities. Conﬁg1-3 are strictly read-only. The few writable ﬁelds in Conﬁg — notably Conﬁg[K0] — are there for

historic compatibility, and are typically written once soon after bootstrap and never changed again.

The 24K core also deﬁnes Conﬁg7 for some implementation-speciﬁc settings (which most programmers will never

use).

Broadly speaking the registers have these roles:

While initializing your CPU you might also want to look at the EBase register, which can be used to relocate your

exception entry points: see Figure 5.2 and the text round it.

2.1.1 The Conﬁg register

Figure 2.1 Fields in the Conﬁg Register

In Figure 2.1:

M: reads 1 if Conﬁg1 is available (it always is).

Table 2.1 Roles of Conﬁg registers

Conﬁg A mix of historical and CPU-dependent information, described in Figure 2.1 below. Some

ﬁelds are writable.

Conﬁg1 Read-only, strictly to the MIPS32 architecture. Conﬁg1 shows the primary cache conﬁgura-

tion and basic CPU capabilities, while Conﬁg2 shows information about L2 and L3 caches, if

ﬁtted (the L2 cache is optional and the L3 cache is unavailable in 24K family cores). Shown in

Figure 2.2 and Figure 2.3 below.

Conﬁg2

Conﬁg3 Read-only, strictly to Release 2 of the [MIPS32] architecture.

More CPU capability information.

Conﬁg7 24K-core-speciﬁc, with both read-only and writable ﬁelds. It’s a strong convention that the

writable ﬁelds should default to “expected” behavior, so beginners may simply leave these

ﬁelds alone. The ﬁelds are described later, in Section B.4.5 “The Config7 register”.

31 30 28 27 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 9 7 6 4 3 2 0

M K23 KU ISP DSP UDI SB 0 WC MM 0 BM BE AT AR MT 0 VI K0

12 2 01 0 1 02

2.1 Probing your CPU - Config CP0 registers

Programming the MIPS32® 24K® Core Family, Revision 04.63 18

K23, KU, K0: set the cacheability attributes of chunks of the memory map by writing these fields. All share a 3-bit

encoding with the cacheability ﬁeld found in TLB entries, which is described in Table 3.3 in Section

3.4.2 “Cacheability options”.

Conﬁg[K0] sets the cacheability of kseg0, but it would be very unusual to make that anything other than cacheable

(on different, cache-coherent CPUs, it may want to be set to cacheable-coherent). The power-on value of this standard

ﬁeld is not mandated by the [MIPS32] architecture; but the 24K core follows the recommendation to set it to "2",

making "kseg0" uncached. That can be surprising; early system initialization software typically re-writes it to "3" in

order that kseg0 will be cached, as expected.

If your 24K core-based system uses fixed mapping instead of having a TLB, Conﬁg[K23] is for program addresses

0xC000.0000-0xFFFF.FFFF (the “kseg2” and “kseg3” areas), while Conﬁg[KU] is for program addresses

0x0000.0000-0x7FFF.FFFF (the “kuseg” area). If you have a TLB, these regions are mapped and these ﬁelds are

unused (write only zeroes to them).

ISP, DSP: read 1 if I-side and/or D-side scratchpad (SPRAM) is ﬁtted, see Section 3.6, "Scratchpad memory/

SPRAM".

(Don’t confuse this with the MIPS DSP ASE, whose presence is indicated by Conﬁg3[DDSP].)

UDI: reads 1 if your core implements user-deﬁned "CorExtend" instructions. “CorExtend” is available on cores whose

name ends in "Pro".

SB: read-only "SimpleBE" bus mode indicator. If set, means that this core will only do simple partial-word transfers on

its OCP interface; that is, the only partial-word transfers will be byte, aligned half-word and aligned word.

If zero, it may generate partial-word transfers with an arbitrary set of bytes enabled (which some memory controllers

may not like).

WC: Warning: this is a diagnostic/test ﬁeld, not intended for customer use, and may vanish without notice from a

future version of the core.

Set this 1 to make the Conﬁg1[IS] and Conﬁg1[DS] ﬁelds writable, which allows you to reduce the number of avail-

able L1 I- and D-cache ``sets per way'', and shrink the usable cache size. You'd never want to do this in a real system,

but it is conceivable it might be useful for debug or performance analysis.

MM: writable: set 1 if you want writes resulting from separate store instructions in write-through mode merged into a

single (possibly burst) transaction at the interface. This has no affect on cache writebacks (which are always whole

blocks together) or uncached writes (which are never merged).

BM: read-only - tells you whether your bus uses sequential or sub-block burst order; set by hardware to match your sys-

tem controller.

BE: reads 1 for big-endian, 0 for little-endian.

AT: MIPS32 or MIPS64 compliance On 24K family cores it will read “0”, but the possible values are:

0 MIPS32

1 MIPS64 instruction set but MIPS32 address map

2 MIPS64 instruction set with full address map

Initialization and identity

19 Programming the MIPS32® 24K® Core Family, Revision 04.63

AR: Architecture revision level. On 24K family cores it will read “1”, denoting release 2 of the MIPS32 specification.

MT: MMU type (all MIPS Technologies cores may be conﬁgured as type 1 or 3):

VI: 1 if the L1 I-cache is virtual (both indexed and tagged using virtual address). No contemporary MIPS Technologies

core has a virtual I-cache.

K0: as described in the notes above on Conﬁg[K23] etc, this ﬁeld determines the cacheing behaviour of the ﬁxed kseg0

memory region .

2.1.2 The Conﬁg1-2 registers

These two read-only registers tell you the size of the TLB, and the size and organization of L1, L2 and L3 caches (a

zero “line size” is used to indicate a cache which isn’t there). They’re best described together.

Conﬁg1 has some ﬁelds which tell you about the presence of some of the older extensions to the base MIPS32 archi-

tecture are implemented on this core. These bits ran out, and other extensions are noted in Conﬁg3.

Figure 2.2 Fields in the Conﬁg1 Register

Figure 2.3 Fields in the Conﬁg2 Register

Conﬁg1[M]: continuation bit, 1 if Conﬁg2 is implemented.

Conﬁg1[MMUSize]: the size of the TLB array (the array has MMUSize+1 entries).

Conﬁg1[IS,IL,IA,DS,DL,DA]: for each cache this reports

So if (IS, IL, IA) is (2,4,3) you have 256 sets/way, 32 bytes per line and 4-way set associative: that’s a 32Kbyte cache.

0 MIPS32/MIPS64 Release 1

1 MIPS32/MIPS64 Release 2

0 None

1 MIPS32/64 compliant TLB

2 “BAT” type

3 MIPS-standard ﬁxed mapping

31 30 25 24 22 21 19 18 16 15 13 12 10 9 7 6 5 4 3 2 1 0

M MMUSize IS IL IA DS DL DA C2 MD PC WR CA EP FP

1434301111

31 30 28 27 24 23 20 19 16 15 13 12 11 8 7 4 3 0

M TU TS TL TA SU SS SL SA

10 0 0 0 0

Number of sets per way. Calculate as: 64 × 2

Line size. Zero means no cache at all, otherwise calculate as: 2 × 2

A Associativity/number of ways - calculate as A + 1

2.1 Probing your CPU - Config CP0 registers

Programming the MIPS32® 24K® Core Family, Revision 04.63 20

Conﬁg1[C2,FP]: 1 if coprocessor 2 or or an FPU (coprocessor 1) ﬁtted, respectively. A coprocessor 2 would be a cus-

tomer-designed coprocessor.

Conﬁg1[MD]: 1 if MDMX ASE is implemented in the ﬂoating point unit (very unlikely for the 24K core).

Conﬁg1[PC]: there is at least one performance counter implemented, see Section 7.4 “Performance counters”.

Conﬁg1[WR]: reads 1 because the 24K core always has watchpoint registers, see Section 7.3 “CP0 Watchpoints”.

Conﬁg1[CA]: reads 1 because the MIPS16e compressed-code instruction set is available (as it generally is on MIPS

Technologies cores).

Conﬁg1[EP]: reads 1 because an EJTAG debug unit is always provided, see Section 7.1, "EJTAG on-chip debug unit".

Conﬁg2[M]: continuation bit, 1 if Conﬁg3 is implemented.

Conﬁg2[TU]: implementation-speciﬁc bits related to tertiary cache, if ﬁtted. Can be writable.

Conﬁg2[TS,TL,TA]: tertiary cache size and shape - encoded just like Conﬁg1[IS,IL,IA] which see above.

Conﬁg2[SU]: implementation-speciﬁc bits for secondary cache, if ﬁtted. Can be writable.

Conﬁg2[SS,SL,SA]: secondary cache size and shape, encoded like Conﬁg1[IS,IL,IA] above.

2.1.3 The Conﬁg3 register

Conﬁg3 provides information about the presence of optional extensions to the base MIPS32 architecture. A few of

them were in Conﬁg2, but that ran out of bits.

Figure 2.4 Fields in the Conﬁg3 Register

Fields shown in Figure 2.4 include:

Conﬁg3[M]: continuation bit, zero because there is no Conﬁg4.

Config3[ULRI]: reads 1 if the core implements the UserLocal register, typically used by software threads packages.

More information in Section B.4.2 “The UserLocal register”.

DSP2P, DSPP: DSPP reads 0 because the MIPS DSP extension is not available for this CPU. DSP2P distinguishes

revision 2 of the DSP ASE .

VEIC: read-only bit from the core input signal SI_EICPresent which should be set in the SoC to alert software to the

availability of an EIC-compatible interrupt controller, see Section 5.2, "MIPS32® Architecture Release 2 - enhanced

interrupt system(s)".

VInt: reads 1 to tell you that the 24K core can handle vectored interrupts.

SP: reads 0 to tell you the 24K core does not support sub-4Kbyte page sizes.

31 30 14 13 12 11 10 9 7 6 5 4 3 2 1 0

M 0 ULRI 0

DSP2P

DSPP 0 VEIC VInt SP 0 MT SM TL

0 0 10 00

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