"STM32H750xB和STM32H753xI单片机的局限性及解决方案"

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This document, titled "ES0396_STM32H750xB and STM32H753xI Single Chip Microcontroller Limitations," outlines the limitations and errata associated with the STM32H750xB and STM32H753xI devices as of June 2019. The document provides an in-depth analysis of the specific part numbers and their variants, along with workarounds for the device limitations outlined in the device datasheet and reference manual RM0433. Section 1 of the document offers a comprehensive summary of the limitations and errata associated with the STM32H750xB and STM32H753xI devices, while Section 2 provides detailed descriptions of workarounds for these limitations. The document aims to assist users in navigating and mitigating the constraints of these single chip microcontrollers, ensuring smoother and more efficient operation of the devices. The applicability of this document pertains to the part numbers of STM32H750xB and STM32H753xI devices, as listed in Table 1, and their respective variants displayed in Table 2. The limitations and workarounds detailed in this document are specifically tailored to these part numbers and variants, offering valuable insights for users working with these specific devices. In conclusion, "ES0396_STM32H750xB and STM32H753xI Single Chip Microcontroller Limitations" serves as a comprehensive guide for understanding and addressing the limitations of the STM32H750xB and STM32H753xI devices. By providing detailed information and workarounds, this document empowers users to effectively navigate and optimize the performance of these single chip microcontrollers, ultimately enhancing their overall functionality and efficiency.

ES0396 Rev 6 7/40

STM32H750xB/753xI Summary of device limitations

System

2.2.1 Timer system breaks do not work N--

2.2.2 Clock recovery system synchronization with USB SOF does not work A--

2.2.3 SysTick external clock is not HCLK/8 A--

2.2.4

Option byte loading can be done with the user wait-state

configuration

A--

2.2.5

Flash BusFault address register may not be valid when an ECC

double error occurs

A--

2.2.6 Flash ECC address register may not be updated N--

2.2.7 PCROP-protected areas in Flash memory may be unprotected A--

2.2.8

Flash memory bank swapping might impact embedded Flash

memory interface behavior

N--

2.2.9 Reading from AXI SRAM may lead to data read corruption A--

2.2.10 Clock switching does not work when LSE failure is detected by CSS A--

2.2.11

RTC stopped when a system reset occurs while the LSI is used as a

clock source

A--

2.2.12 USB OTG_FS PHY drive limit on DP/DM pins N--

2.2.13 Unexpected leakage current on I/Os when VIN higher that VDD A--

2.2.14 LSE oscillator driving capability selection bits are swapped A--

2.2.15 HRTIM internal synchronization does not work N--

2.2.16

Device stalled when two consecutive level regressions occur without

accessing from/to backup SRAM

-AA

2.2.17 Invalid Flash memory CRC P--

2.2.18

GPIO assigned to DAC cannot be used in output mode when the

DAC output is connected to on-chip peripheral

NNN

2.2.19 Unstable LSI when it clocks RTC or CSS on LSE AAA

2.2.20 480 MHz maximum CPU frequency not available on silicon revision Y PPP

ADC

2.3.1 Conversion overlap may impact the ADC accuracy A--

2.3.2 ADC resolution limited by LSE activity A--

2.3.3 ADC maximum sampling rate when VDDA is lower than 2 V A--

2.3.4 ADC maximum resolution when VDDA is higher than 3.3 V A--

2.3.5 First ADC injected conversion in a sequence may be corrupted A--

2.3.6

Writing the ADC_JSQR register when JADCSTART = 1 and

JQDIS = 1 may lead to incorrect behavior

A--

2.3.7 Conversion may be triggered by context queue register update AAA

2.3.8

Updated conversion sequence may be trigged by context queue

update

AAA

Table 3. Summary of device limitations (continued)

Function Section Limitation

Status

Rev. Y

Rev.

(1)

Rev.

Summary of device limitations STM32H750xB/753xI

8/40 ES0396 Rev 6

OPAMP 2.4.1 OPAMP high-speed mode must not be used N--

FMC

2.5.1 Dummy read cycles inserted when reading synchronous memories NNN

2.5.2 Wrong data read from a busy NAND Flash memory AAA

2.5.3 Missed clocks with continuous clock feature enabled A--

QUADSPI

2.6.1 First nibble of data is not written after a dummy phase A--

2.6.2 QUADSPI_CCR hangs when QUADSPI_CR is cleared AAA

2.6.3

QUADSPI cannot be used in Indirect read mode when only data

phase is activated

AAA

LCD-TFT 2.7.1

Device stalled when accessing LTDC registers while pixel clock is

disabled

AAA

LPTIM 2.8.1 MCU may remain stuck in LPTIM interrupt when entering Stop mode A--

RTC 2.9.1 RTC calendar registers are not locked properly A--

I2C

2.10.1

10-bit master mode: new transfer cannot be launched if first part of

the address is not acknowledged by the slave

AAA

2.10.2

Wrong behavior in Stop mode when wakeup from Stop mode is

disabled in I2C

AAA

2.10.3

Wrong data sampling when data setup time (tSU;DAT) is shorter than

one I2C kernel clock period

P--

2.10.4 Spurious bus error detection in Master mode AAA

2.10.5 Last-received byte loss in Reload mode P--

2.10.6 Spurious master transfer upon own slave address match PPP

2.10.7 START bit is cleared upon setting ADDRCF, not upon address match PPP

USART 2.11.1

Underrun flag is set when the USART is used in SPI Slave receive

mode

AAA

SPI

2.11.1 Spurious DMA Rx transaction after simplex Tx traffic A--

2.12.2 Master data transfer stall at system clock much faster than SCK AAA

2.12.3 Corrupted CRC return at non-zero UDRDET setting PPP

2.12.4 TXP interrupt occurring while SPI/I2Sdisabled AAA

SDMMC

2.13.1

Busy not detected when a write operation suspended during busy

phase resumes

A--

2.13.2

Wrong data line 2 generation between two blocks during DDR

transfer with Read wait mode enabled

A--

2.13.3

Unwanted overrun detection when an AHB error is reported whereas

all bytes have been received

A--

2.13.4 Consecutive multiple block transfers can induce incorrect data length A--

2.13.5 Clock stop reported during Read wait mode sequence A--

Table 3. Summary of device limitations (continued)

Function Section Limitation

Status

Rev. Y

Rev.

(1)

Rev.

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