MCF52259冷火鸡微控制器：高性能、低功耗特性概述

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"MCF52259是一款基于ColdFire®家族的32位微控制器，由Freescale Semiconductor制造。该系列包括MCF52252、MCF52254、MCF52255、MCF52256、MCF52258和MCF52259设备，设计有高度集成和多样化的特点。这款32位设备采用Version 2 ColdFire内核，工作频率高达80MHz，提供高性能和低功耗。其内置存储器包括最多512KB的闪存和64KB的静态随机访问内存（SRAM）。此外，还集成了多种片上模块，如增强型中断控制器、串行通信接口、模拟功能等。" MCF52259微控制器系列是冷火（ColdFire）家族的一部分，这是一个基于RISC（精简指令集计算）架构的处理器系列。该系列的每个器件都具有不同的性能和功能配置，以满足不同应用的需求。MCF52259采用Version 2 ColdFire核心，能在内部闪存上运行时达到76 MIPS（Dhrystone 2.1）的性能，且工作频率最高可达80MHz，确保了高效运算能力。在内存方面，MCF52259提供了丰富的存储解决方案，包括大容量的闪存和SRAM。高达512KB的闪存可以用于存储程序代码和固件，而64KB的SRAM则用于临时数据存储和快速访问，这样的组合优化了程序执行速度和系统响应。此外，MCF52259集成了多个片上模块，以增强其功能。例如，增强型中断控制器（EIC）能够处理复杂的中断管理，提高系统的实时性。串行通信接口（如UART或SPI）使得与其他设备的通信变得简单且灵活。模拟功能可能包括模数转换器（ADC）、数模转换器（DAC）和其他模拟接口，这些对于处理混合信号应用非常有用。封装选项包括LQFP-144、LQFP-100和MAPBGA-144，尺寸分别为20mmx20mm、14mmx14mm和13mmx13mm，满足不同尺寸和引脚数量的硬件设计需求。这些封装设计允许MCF52259适用于各种嵌入式系统，如工业控制、汽车电子、消费电子产品等。 MCF52259是一款强大且灵活的32位微控制器，具备高效的处理能力、丰富的内置资源和多样化的封装选择，是嵌入式系统设计中的理想选择。由于Freescale Semiconductor保留了更改规格的权利，设计者在使用时应参考最新的数据手册以获取最新的技术信息和更新。

Family Configurations

MCF52259 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor 8

— Pre-divider capable of dividing the clock source frequency into the PLL reference frequency range

— System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator

— Low power modes supported

—2

(0  n  15) low-power divider for extremely low frequency operation

• Interrupt controller

— Uniquely programmable vectors for all interrupt sources

— Fully programmable level and priority for all peripheral interrupt sources

— Seven external interrupt signals with fixed level and priority

— Unique vector number for each interrupt source

— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)

— Support for hardware and software interrupt acknowledge (IACK) cycles

— Combinatorial path to provide wake-up from low-power modes

• DMA controller

— Four fully programmable channels

— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (432-bit)

burst transfers

— Source/destination address pointers that can increment or remain constant

— 24-bit byte transfer counter per channel

— Auto-alignment transfers supported for efficient block movement

— Bursting and cycle-steal support

— Software-programmable DMA requests for the UARTs (3) and 32-bit timers (4)

— Channel linking support

• Reset

— Separate reset in and reset out signals

— Seven sources of reset:

– Power-on reset (POR)

– External

–Software

– Watchdog

– Loss of clock / loss of lock

– Low-voltage detection (LVD)

–JTAG

— Status flag indication of source of last reset

• Chip configuration module (CCM)

— System configuration during reset

— Selects one of six clock modes

— Configures output pad drive strength

— Unique part identification number and part revision number

• General purpose I/O interface

— Up to 56 bits of general purpose I/O on 100-pin package

— Up to 96 bits of general purpose I/O on 144-pin package

— Bit manipulation supported via set/clear functions

— Programmable drive strengths

— Unused peripheral pins may be used as extra GPIO

• JTAG support for system level board testing

MCF52259 ColdFire Microcontroller, Rev. 4

Family Configurations

Freescale Semiconductor9

1.2.2 V2 Core Overview

The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage

instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is

a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP).

The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage

(AGEX) performs instruction execution and calculates operand effective addresses, if needed.

The V2 core implements the ColdFire instruction set architecture revision A+ with support for a separate user stack pointer

register and four new instructions to assist in bit processing. Additionally, the core includes the enhanced multiply-accumulate

(EMAC) unit for improved signal processing capabilities. The EMAC implements a three-stage arithmetic pipeline, optimized

for 32x32 bit operations, with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and

unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The EMAC

provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost.

1.2.3 Integrated Debug Module

The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator

development tools. Through a standard debug interface, access to debug information and real-time tracing capability is provided

on 144-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit

emulators.

The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register,

a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the

dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint

registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or

dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.

This device implements revision B+ of the ColdFire Debug Architecture.

The processor’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be

serviced while processing a debug interrupt event. This ensures the system continues to operate even during debugging.

To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports.

These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining

processor activity at the CPU’s clock rate. The device includes a new debug signal, ALLPST. This signal is the logical AND of

the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).

The full debug/trace interface is available only on the 144-pin packages. However, every product features the dedicated debug

serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.

1.2.4 JTAG

The processor supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action

Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and

three test registers (a 1-bit bypass register, a boundary-scan register, and a 32-bit ID register). The boundary scan register links

the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system

logic.

The device implementation can:

• Perform boundary-scan operations to test circuit board electrical continuity

• Sample system pins during operation and transparently shift out the result in the boundary scan register

• Bypass the device for a given circuit board test by effectively reducing the boundary-scan register to a single bit

• Disable the output drive to pins during circuit-board testing

• Drive output pins to stable levels

Family Configurations

MCF52259 ColdFire Microcontroller, Rev. 4

Freescale Semiconductor 10

1.2.5 On-Chip Memories

1.2.5.1 SRAM

The dual-ported SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access in a

single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the 4-Gbyte address space. This

memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM module is

physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or

memory-referencing commands from the debug module.

The SRAM module is also accessible by the DMA, FEC, and USB. The dual-ported nature of the SRAM makes it ideal for

implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of

the SRAM to maximize system performance.

1.2.5.2 Flash Memory

The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local

bus. The CFM is constructed with four banks of 64-Kbyte16-bit flash memory arrays to generate 512 Kbytes of 32-bit flash

memory. These electrically erasable and programmable arrays serve as non-volatile program and data memory. The flash

memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring

an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller

that supports interleaved accesses from the 2-cycle flash memory arrays. A backdoor mapping of the flash memory is used for

all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be

programmed via the EzPort, which is a serial flash memory programming interface that allows the flash memory to be read,

erased and programmed by an external controller in a format compatible with most SPI bus flash memory chips.

1.2.6 Cryptographic Acceleration Unit

The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, the CAU is a coprocessor

tightly-coupled to the V2 ColdFire core that implements a set of specialized operations to increase the throughput of

software-based encryption and message digest functions, specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms.

Second, a random number generator provides FIPS-140 compliant 32-bit values to security processing routines. Both modules

supply critical acceleration to software-based cryptographic algorithms at a minimal hardware cost.

1.2.7 Power Management

The device incorporates several low-power modes of operation entered under program control and exited by several external

trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the supply

voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or interrupt

condition if it falls below the LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the

chip falls below the standby battery voltage.

1.2.8 FlexCAN

The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts A and B. The CAN

protocol can be used as an industrial control serial data bus, meeting the specific requirements of reliable operation in a harsh

EMI environment with high bandwidth. This instantiation of FlexCAN has 16 message buffers.

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MCF52259冷火鸡微控制器：高性能、低功耗特性概述

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