3D IC中热敏P/G TSV规划降低IR压降的新方法

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"这篇文章主要探讨了在3D集成电路(3D IC)中，如何通过热敏P/G TSV(电源/接地通孔)规划来有效降低IR压降问题。随着3D集成技术的发展，芯片上的温度升高会导致导线电阻增加和漏电流增加，从而加剧IR压降。因此，在设计中考虑热效应对于电源/接地网络至关重要。作者Zuowei Liu等人提出了一种创新的热感知P/G TSV规划算法，该算法利用考虑了温度相关泄漏电流的敏感度模型。传统的3D设计通常采用统一的P/G网格结构，但这种方法未能充分利用P/G TSV的潜力。新算法则允许非均匀的P/G网格拓扑，即允许短线将P/G TSV连接到P/G网格，以优化整个PIG(电源/接地)网络。理论分析和实际实验结果显示，忽视热效应可能导致IR压降低估约11%。解决严重的IR压降问题，与不考虑热影响相比，可能需要增加51.8%的P/G TSV数量。同时，基于敏感度模型的P/G TSV规划能有效降低最大IR压降42.3%，并减少82.4%的被侵犯节点数。这些改进对于提高3D IC的性能和能效具有重要意义。关键词包括：热效应、电源/接地网络、IR压降、TSV(通孔)、3D集成电路。这项研究为3D IC设计提供了一个新的思路，即通过热敏P/G TSV规划来优化电源分配，降低IR压降，提升系统整体性能。" 在3D IC设计中，理解并解决IR压降是关键挑战之一，因为这直接影响到芯片的运行速度和功耗。通过热敏P/G TSV规划，设计者能够更好地控制温度分布，从而改善电源效率，减少功率损耗，同时提高系统的可靠性和稳定性。这种技术的应用对于未来的高性能计算和移动设备等高密度集成芯片设计具有重要价值。

Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs

Zuowei Li

, Yuchun Ma

, Qiang Zhou

, Yici Cai

, Yuan Xie

, Tingting Huang

Department of Computer Science and Technology, Tsinghua University, Beijing

Pennsylvania State University, USA

National Tsinghua University, Taiwan

article info

Available online 26 May 2012

Keywords:

Thermal

Power/Ground network

IR drop

TSV

3D IC

abstract

With the leakage-thermal dependency, the increasing on-chip temperature in 3D designs has serious

impact on IR drop due to the increased wire resistance and increased leakage current. Therefore, it is

necessary to consider Power/Ground network design with thermal effects in 3D designs. Though Power/

Ground (P/G) TSV can help to relieve the IR drop violation by vertically connecting on-chip P/G

networks on different layers, most previous work restricts the uniform P/G grids so that the potential of

P/G TSV planning has not been fully explored. In this paper, we present an efﬁcient thermal-aware P/G

TSV planning algorithm based on a sensitivity model with temperature-dependent leakage current

considered. Non-uniform P/G grid topology is explored to optimize the P/G network by allowing short

wires to connect the P/G TSVs to P/G grids. Both the theoretical analysis and experimental results show

the efﬁciency of our approach. Results show that neglecting thermal impacts on power delivery can

underestimate IR drop by about 11%. To relieve the severe IR drop violation, 51.8% more P/G TSVs are

needed than the cases without thermal impacts considered. Results also show that our P/G TSV

planning based on the sensitivity model can reduce m ax IR drop by 42.3% and reduce the number of

violated nodes by 82.4%.

1. Introduction

Recently, through-silicon via (TSV) based 3D IC designs emerge

as a promising solution because of many beneﬁts such as wire

length reduction, smaller form factors, and heterogeneous inte-

gration [1–4]. Due to the increased power density, the tempera-

ture distribution varies a lot between layers in 3D chips. The

imbalance of power distribution among layers results in not only

the various temperature distributions, but also quite different

distributions of IR drops on different layers. The power grid on a

layer is usually a metal mesh. It distributes power and ground

voltages from pad locations to chip cells. Currents drawn from the

package pads ﬂow on the metal stripes to current loadings. This

will cause some voltage drops (IR drops) on the branch because of

the metal resistance. In 3D ICs, it tends to appear different IR

drops on different layers. Under such circumstance, P/G TSVs can

be allocated between adjacent layers to relieve the IR drop

violations. According to different fabrication processes, as

shown in Fig.1, the P/G-network structures in 3D ICs can be

classiﬁed into three major schemes: (a) connected (P/G TSVs are

used to connect different P/G networks on adjacent layers);

(b) non-connected (P/G network on each layer is connected to

the package IO directly by wire bonding, there is no directed

connection between P/G networks); and (c) a combination of

connected and non-connected P/G networks. It is obvious that

In this work, we focus on the structure as shown in Fig.1(c).

Therefore, the P/G network design in 3D ICs is no longer several

separated 2D designs on an individual layer, but a 3D P/G network

should be constructed with P/G TSVs so that the IR drop

distribution on multiple layers can be optimized at the same

time. Currently, only a few works have explored 3D P/G network

design. The related works can be divided into two categories by

their optimization objectives. The ﬁrst category focuses on the

reduction of power supply noise [5–13]. For example, decoupling

capacitors (decaps) can be used during placement to reduce the

power supply noise [5–9]. In addition to using decaps to reduce

P/G noise, the density of P/G TSVs can be adjusted to reduce the

power supply noise [13]. The second category considers the IR

drop in 3D ICs during early stages. A 3D ﬂoorplan and P/G

network co-synthesis tool was proposed to explore the ﬂoor-

planning and P/G network topology design with IR drop con-

straint considered [14]. Since TSVs go through the silicon layer,

the distribution of P/G TSVs is inﬂuenced by not only the power

distribution but also the whitespace distribution around circuit

modules. In this paper, we further explore P/G TSV planning

Contents lists available at SciVerse ScienceDirect

journal homepage: www.elsevier.com/locate/vlsi

INTEGRATION, the VLSI journal

http://dx.doi.org/10.1016/j.vlsi.2012.05.002

Corresponding author.

E-mail address: myc@mail.tsinghua.edu.cn (Y. Ma).

INTEGRATION, the VLSI journal 46 (2013) 1–9

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