STM32F401CCU6微控制器详细规格：高效能，Cortex-M4内核，FPU支持

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"STM32F401CCU6是一款由STMicroelectronics生产的微控制器，基于ARM Cortex-M4 32位处理器，带有浮点运算单元（FPU）和动态效率线性（Dynamic Efficiency Line），支持批量采集模式（BAM）。这款芯片的工作电压范围在1.7V至3.6V之间，工作温度范围覆盖-40°C到85/105/125°C。STM32F401CCU6具有高性能的特性，如高达84MHz的时钟频率、零等待状态执行Flash内存的适应性实时加速器（ART Accelerator）、内存保护单元以及数字信号处理指令。其内存配置包括最大256KB的闪存、512字节的OTP内存和最多64KB的SRAM。此外，该芯片还集成了多种时钟、复位和电源管理功能，如上电复位（POR）、掉电复位（PDR）、电压检测器（PVD）和过压复位（BOR），并支持不同频率的晶体振荡器和内部RC振荡器。在低功耗方面，STM32F401CCU6在运行模式下每MHz的电流消耗为128µA，在停止模式（Flash保持在停止模式，快速唤醒时间）下的典型电流消耗为42µA@25°C，最大65µA@25°C。" STM32F401CCU6的数据手册详细介绍了该微控制器的各项功能和特性，对于开发者来说，是理解和使用该芯片的关键资源。手册中通常会涵盖以下内容： 1. **引脚描述**：列出所有引脚的功能，包括GPIO、外设接口等，并提供封装图。 2. **外设集成**：详述集成的定时器（TIMs）、模数转换器（ADC）、通信接口（如UART、SPI、I2C等）和其他外设的特性、工作模式和使用方法。 3. **存储器布局**：详细说明Flash和SRAM的地址空间、读写速度、保护机制等。 4. **时钟系统**：解释不同的时钟源、分频器和时钟树结构，以及如何配置时钟系统。 5. **电源管理**：描述各种电源模式，如运行、休眠、停止和待机模式，以及相应的电流消耗。 6. **中断和事件处理**：列出所有可用的中断源，以及中断向量表。 7. **开发工具和调试支持**：可能包括JTAG、SWD调试接口的信息，以及如何使用IDE和仿真器。 8. **安全和保护特性**：如内存保护单元（MPU）、Bootloader安全特性、密码保护等。 9. **温度和电气特性**：给出工作和存储温度范围，以及I/O口的电压等级和电流驱动能力。 10. **应用示例**：提供基本的电路连接示例和代码片段，帮助开发者快速上手。数据手册还会包含故障排查指南、电气特性表、封装和热特性等信息，确保开发者能够全面了解和有效利用STM32F401CCU6微控制器。在实际项目中，通过深入研究这些内容，可以充分发挥芯片的性能，实现高效、可靠的嵌入式系统设计。

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Functional overview STM32F401xB STM32F401xC

16/139 DocID024738 Rev 10

3.4 Embedded Flash memory

The devices embed up to 256 Kbytes of Flash memory available for storing programs and

data.

3.5 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a software

signature during runtime, to be compared with a reference signature generated at link-time

and stored at a given memory location.

3.6 Embedded SRAM

All devices embed:

• Up to 64 Kbytes of system SRAM which can be accessed (read/write) at CPU clock

speed with 0 wait states

3.7 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves

(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient

operation even when several high-speed peripherals work simultaneously.

Figure 4. Multi-AHB matrix

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DocID024738 Rev 10 17/139

STM32F401xB STM32F401xC Functional overview

3.8 DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8

streams each. They are able to manage memory-to-memory, peripheral-to-memory and

memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,

support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is

needed when the controller reaches the end of the buffer. The two DMA controllers also

have a double buffering feature, which automates the use and switching of two memory

buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software

trigger on each stream. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals:

• SPI and I

• I

• USART

• General-purpose, basic and advanced-control timers TIMx

• SD/SDIO/MMC host interface

• ADC

3.9 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the Cortex



M4 with FPU.

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving, higher-priority interrupts

• Support tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt

latency.

3.10 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 21 edge-detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 81 GPIOs can be connected

to the 16 external interrupt lines.

Functional overview STM32F401xB STM32F401xC

18/139 DocID024738 Rev 10

3.11 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The

application can then select as system clock either the RC oscillator or an external 4-26 MHz

clock source. This clock can be monitored for failure. If a failure is detected, the system

automatically switches back to the internal RC oscillator and a software interrupt is

generated (if enabled). This clock source is input to a PLL thus allowing to increase the

frequency up to 84 MHz. Similarly, full interrupt management of the PLL clock entry is

available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB

buses is 84 MHz while the maximum frequency of the high-speed APB domains is 84 MHz.

The maximum allowed frequency of the low-speed APB domain is 42 MHz.

The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class

performance. In this case, the I

S master clock can generate all standard sampling

frequencies from 8 kHz to 192 kHz.

3.12 Boot modes

At startup, boot pins are used to select one out of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

The bootloader is located in system memory. It is used to reprogram the Flash memory by

using either USART1(PA9/10), USART2(PD5/6), USB OTG FS in device mode (PA11/12)

through DFU (device firmware upgrade), I2C1(PB6/7), I2C2(PB10/3), I2C3(PA8/PB4),

SPI1(PA4/5/6/7), SPI2(PB12/13/14/15) or SPI3(PA15, PC10/11/12).

For more detailed information on the bootloader, refer to Application Note: AN2606, STM32

microcontroller system memory boot mode.

3.13 Power supply schemes

• V

= 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor

(POR/PDR) disabled, provided externally through V

pins. Requires the use of an

external power supply supervisor connected to the VDD and PDR_ON pins.

• V

= 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when

enabled), provided externally through V

pins.

• V

SSA

, V

DDA

= 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs

and PLL. V

DDA

and V

SSA

must be connected to V

and V

, respectively, with

decoupling technique.

• V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when V

is not present.

Refer to Figure 18: Power supply scheme for more details.

DocID024738 Rev 10 19/139

STM32F401xB STM32F401xC Functional overview

3.14 Power supply supervisor

3.14.1 Internal reset ON

This feature is available for V

operating voltage range 1.8 V to 3.6 V.

The internal power supply supervisor is enabled by holding PDR_ON high.

The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry

coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and

ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is

reached, the option byte loading process starts, either to confirm or modify default

thresholds, or to disable BOR permanently. Three BOR thresholds are available through

option bytes.

The devices remain in reset mode when V

is below a specified threshold, V

POR/PDR

BOR

, without the need for an external reset circuit.

The devices also feature an embedded programmable voltage detector (PVD) that monitors

the V

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be

generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

higher than the V

PVD

threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

3.14.2 Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal power-on

reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to

low.

An external power supply supervisor should monitor V

and should maintain the device in

reset mode as long as V

is below a specified threshold. PDR_ON should be connected to

this external power supply supervisor. Refer to Figure 5: Power supply supervisor

interconnection with internal reset OFF.

Figure 5. Power supply supervisor interconnection with internal reset OFF

(1)

1. The PRD_ON pin is only available on the WLCSP49 and UFBGA100 packages.

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