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2017-04-24 - Leopard Gecko Family - d0183_Rev1.2 20
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The Cortex-M3, the DMA Controller, and the peripherals run on clocks that can be prescaled separately.
When accessing a peripheral which runs on a frequency equal to or faster than the HFCORECLK, the
number of wait cycles per access, in addition to master arbitration, is given by:
Memory Wait Cycles with Clock Equal or Faster than HFCORECLK
N
cycles
= 2 + N
slave cycles
, (5.3)
where N
slave cycles
is the wait cycles introduced by the slave.
When accessing a peripheral running on a clock slower than the HFCORECLK, wait-cycles are
introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per
access, in addition to master arbitration, is given by:
Memory Wait Cycles with Clock Slower than CPU
N
cycles
= (2 + N
slave cycles
) x f
HFCORECLK
/f
HFPERCLK
, (5.4)
where N
slave cycles
is the number of wait cycles introduced by the slave.
For general register access, N
slave cycles
= 1.
More details on clocks and prescaling can be found in Chapter 11 (p. 124) .
5.3 Access to Low Energy Peripherals (Asynchronous Registers)
5.3.1 Introduction
The Low Energy Peripherals are capable of running when the high frequency oscillator and core system
is powered off, i.e. in energy mode EM2 and in some cases also EM3. This enables the peripherals to
perform tasks while the system energy consumption is minimal.
The Low Energy Peripherals are:
• Liquid Crystal Display driver - LCD
• Low Energy Timer - LETIMER
• Low Energy UART - LEUART
• Pulse Counter - PCNT
• Real Time Counter - RTC
• Watchdog - WDOG
• Low Energy Sensor Interface - LESENSE
• Backup RTC - BURTC
All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low
Energy Peripherals are running on clocks asynchronous to the core clock, there are some constraints
on how register accesses can be done, as described in the following sections.
5.3.1.1 Writing
Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into
the Low Energy clock domain to maintain data consistency and predictable operation. There are two
different synchronization mechanisms on the Leopard Gecko; immediate synchronization, and delayed
synchronization. Immediate synchronization is available for the RTC, LETIMER and LESENSE, and
results in an immediate update of the target registers. Delayed synchronization is used for the other
Low Energy Peripherals, and for these peripherals, a write operation requires 3 positive edges on the
clock of the Low Energy Peripheral being accessed. Registers requiring synchronization are marked
"Asynchronous" in their description header.
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