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Freescale Semiconductor MPC5604B/C 微控制器参考手册
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"MPC5604BCRM.pdf" 是一份由Freescale Semiconductor(现为NXP Semiconductors)发布的关于MPC5604单片机的详细参考手册,版本为Rev.8.1,发布日期为2012年5月。这份文档包括了MPC5604B/C Microcontroller Reference Manual Addendum (MPC5604B/CRMAD) Rev.1和MPC5604B/C Reference Manual (MPC5604B/CRM) Rev.8两部分。手册的主要目的是提供有关MPC5604B/C微控制器的全面技术信息。
MPC5604是一款基于Power Architecture的微控制器,设计用于汽车电子和其他工业应用。该芯片可能包含了以下关键特性:
1. **处理器核心**: MPC5604B/C可能搭载了高性能的e200z4 Power Architecture核心,支持32位指令集,提供高效的计算能力。
2. **内存结构**: 可能包括嵌入式闪存(Flash Memory)用于存储程序代码和数据,以及SRAM作为高速工作内存。
3. **外设接口**: 微控制器通常集成了多种通信接口,如CAN(Controller Area Network)用于汽车网络,SPI(Serial Peripheral Interface)、I2C(Inter-Integrated Circuit)和UART(Universal Asynchronous Receiver/Transmitter)等串行通信接口。
4. **模拟功能**: 由于其在汽车电子中的应用,MPC5604B/C可能配备了丰富的模拟电路,如ADC(Analog-to-Digital Converter)用于信号采集,以及DAC(Digital-to-Analog Converter)用于信号输出。
5. **定时器和计数器**: 通常包括多个定时器和计数器模块,用于系统控制和事件检测。
6. **电源管理**: 为了适应不同电源条件,MPC5604B/C可能有内置的电源管理单元,支持低功耗模式。
7. **安全特性**: 由于其在关键系统中的应用,该微控制器可能包含硬件安全特性,如加密引擎,以确保代码安全和数据保护。
8. **中断系统**: 支持中断处理,使得系统能够对实时事件做出快速响应。
9. **开发工具支持**: Freescale Semiconductor通常会提供相应的开发工具和软件支持,如CodeWarrior IDE,便于程序员进行应用开发。
手册的修订历史记录了自初次发布以来的更新和修正,以便用户获取最新的技术信息。修订8.2的Addendum详细列出了自修订8以来的改动,用户可以通过访问Freescale的官方网站获取这些更新。
MPC5604B/C是一款专为汽车电子设计的高性能、功能丰富的微控制器,适用于需要强大处理能力和集成度的复杂系统。这份手册是开发人员理解和使用这款微控制器的重要参考资料。
MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 11
22.1.2 FlexCAN module features ............................................................................................424
22.1.3 Modes of operation .......................................................................................................425
22.2 External signal description ............................................................................................................425
22.2.1 Overview ......................................................................................................................425
22.2.2 Signal descriptions ........................................................................................................426
22.3 Memory map and register description ...........................................................................................426
22.3.1 FlexCAN memory mapping .........................................................................................426
22.3.2 Message buffer structure ..............................................................................................428
22.3.3 Rx FIFO structure .........................................................................................................431
22.3.4 Register description ......................................................................................................433
22.4 Functional description ...................................................................................................................451
22.4.1 Overview ......................................................................................................................451
22.4.2 Local priority transmission ...........................................................................................452
22.4.3 Transmit process ...........................................................................................................452
22.4.4 Arbitration process .......................................................................................................453
22.4.5 Receive process ............................................................................................................454
22.4.6 Matching process ..........................................................................................................455
22.4.7 Data coherence .............................................................................................................456
22.4.8 Rx FIFO ........................................................................................................................459
22.4.9 CAN protocol related features ......................................................................................460
22.4.10 Modes of operation details ...........................................................................................464
22.4.11 Interrupts .......................................................................................................................465
22.4.12 Bus interface .................................................................................................................465
22.5 Initialization/Application information ...........................................................................................466
22.5.1 FlexCAN initialization sequence ..................................................................................466
22.5.2 FlexCAN addressing and SRAM size configurations ..................................................467
Chapter 23
Deserial Serial Peripheral Interface (DSPI)
23.1 Introduction ...................................................................................................................................469
23.2 Features .........................................................................................................................................470
23.3 Modes of operation ........................................................................................................................471
23.3.1 Master mode .................................................................................................................471
23.3.2 Slave mode ...................................................................................................................471
23.3.3 Module Disable mode ...................................................................................................471
23.3.4 Debug mode ..................................................................................................................472
23.4 External signal description ............................................................................................................472
23.4.1 Signal overview ............................................................................................................472
23.4.2 Signal names and descriptions ......................................................................................472
23.5 Memory map and register description ...........................................................................................474
23.5.1 Memory map ................................................................................................................474
23.5.2 DSPI Module Configuration Register (DSPIx_MCR) .................................................475
23.5.3 DSPI Transfer Count Register (DSPIx_TCR) ..............................................................478
23.5.4 DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn) .........................478
23.5.5 DSPI Status Register (DSPIx_SR) ...............................................................................486
MPC5604B/C Microcontroller Reference Manual, Rev. 8
12 Freescale Semiconductor
23.5.6 DSPI Interrupt Request Enable Register (DSPIx_RSER) ............................................488
23.5.7 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) .......................................................490
23.5.8 DSPI POP RX FIFO Register (DSPIx_POPR) ............................................................492
23.5.9 DSPI Transmit FIFO Registers 0–3 (DSPIx_TXFRn) .................................................493
23.6 Functional description ...................................................................................................................494
23.6.1 Modes of operation .......................................................................................................495
23.6.2 Start and stop of DSPI transfers ...................................................................................496
23.6.3 Serial peripheral interface (SPI) configuration .............................................................497
23.6.4 DSPI baud rate and clock delay generation ..................................................................500
23.6.5 Transfer formats ...........................................................................................................503
23.6.6 Continuous serial communications clock .....................................................................511
23.6.7 Interrupt requests ..........................................................................................................514
23.6.8 Power saving features ...................................................................................................515
23.7 Initialization and application information .....................................................................................516
23.7.1 How to change queues ..................................................................................................516
23.7.2 Baud rate settings .........................................................................................................516
23.7.3 Delay settings ...............................................................................................................518
23.7.4 Calculation of FIFO pointer addresses .........................................................................518
Chapter 24
Timers
24.1 Introduction ...................................................................................................................................523
24.2 Technical overview ........................................................................................................................523
24.2.1 Overview of the STM ...................................................................................................525
24.2.2 Overview of the eMIOS ...............................................................................................525
24.2.3 Overview of the PIT .....................................................................................................527
24.3 System Timer Module (STM) .......................................................................................................527
24.3.1 Introduction ..................................................................................................................527
24.3.2 External signal description ...........................................................................................528
24.3.3 Memory map and register definition ............................................................................528
24.3.4 Functional description ..................................................................................................532
24.4 Enhanced Modular IO Subsystem (eMIOS) .................................................................................532
24.4.1 Introduction ..................................................................................................................532
24.4.2 External signal description ...........................................................................................535
24.4.3 Memory map and register description ..........................................................................535
24.4.4 Functional description ..................................................................................................547
24.4.5 Initialization/Application information ..........................................................................577
24.5 Periodic Interrupt Timer (PIT) ......................................................................................................580
24.5.1 Introduction ..................................................................................................................580
24.5.2 Features .........................................................................................................................581
24.5.3 Signal description .........................................................................................................581
24.5.4 Memory map and register description ..........................................................................581
24.5.5 Functional description ..................................................................................................586
24.5.6 Initialization and application information ....................................................................587
MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 13
Chapter 25
Analog-to-Digital Converter (ADC)
25.1 Overview .......................................................................................................................................591
25.1.1 Device-specific features ...............................................................................................591
25.1.2 Device-specific implementation ...................................................................................592
25.2 Introduction ...................................................................................................................................592
25.3 Functional description ...................................................................................................................593
25.3.1 Analog channel conversion ..........................................................................................593
25.3.2 Analog clock generator and conversion timings ..........................................................597
25.3.3 ADC sampling and conversion timing .........................................................................597
25.3.4 ADC CTU (Cross Triggering Unit) ..............................................................................599
25.3.5 Presampling ..................................................................................................................600
25.3.6 Programmable analog watchdog ..................................................................................601
25.3.7 Interrupts .......................................................................................................................602
25.3.8 External decode signals delay ......................................................................................603
25.3.9 Power-down mode ........................................................................................................603
25.3.10 Auto-clock-off mode ....................................................................................................603
25.4 Register descriptions .....................................................................................................................604
25.4.1 Introduction ..................................................................................................................604
25.4.2 Control logic registers ..................................................................................................607
25.4.3 Interrupt registers ..........................................................................................................611
25.4.4 Threshold registers .......................................................................................................618
25.4.5 Presampling registers ....................................................................................................619
25.4.6 Conversion timing registers CTR[0..2] ........................................................................622
25.4.7 Mask registers ...............................................................................................................622
25.4.8 Delay registers ..............................................................................................................627
25.4.9 Data registers ................................................................................................................628
Chapter 26
Cross Triggering Unit (CTU)
26.1 Introduction ...................................................................................................................................631
26.2 Main features .................................................................................................................................631
26.3 Block diagram ...............................................................................................................................631
26.4 Memory map and register descriptions .........................................................................................631
26.4.1 Event Configuration Registers (CTU_EVTCFGRx) (x = 0...63) .................................632
26.5 Functional description ...................................................................................................................633
26.5.1 Channel value ...............................................................................................................635
Chapter 27
Flash Memory
27.1 Introduction ...................................................................................................................................639
27.2 Main features .................................................................................................................................640
27.3 Block diagram ...............................................................................................................................640
27.4 Functional description ...................................................................................................................641
27.4.1 Module structure ...........................................................................................................641
MPC5604B/C Microcontroller Reference Manual, Rev. 8
14 Freescale Semiconductor
27.4.2 Flash memory module sectorization .............................................................................642
27.4.3 TestFlash block .............................................................................................................643
27.4.4 Shadow sector ...............................................................................................................645
27.4.5 User mode operation .....................................................................................................645
27.4.6 Reset .............................................................................................................................646
27.4.7 Power-down mode ........................................................................................................647
27.4.8 Low power mode ..........................................................................................................647
27.5 Register description .......................................................................................................................648
27.5.1 CFlash register description ...........................................................................................649
27.5.2 DFlash register description ...........................................................................................680
27.6 Programming considerations .........................................................................................................703
27.6.1 Modify operation ..........................................................................................................703
27.6.2 Double word program ...................................................................................................704
27.6.3 Sector erase ...................................................................................................................706
27.7 Platform flash memory controller .................................................................................................714
27.7.1 Introduction ..................................................................................................................714
27.7.2 Memory map and register description ..........................................................................717
27.8 Functional description ...................................................................................................................726
27.8.1 Access protections ........................................................................................................727
27.8.2 Read cycles – Buffer miss ............................................................................................727
27.8.3 Read cycles – Buffer hit ...............................................................................................727
27.8.4 Write cycles ..................................................................................................................727
27.8.5 Error termination ..........................................................................................................727
27.8.6 Access pipelining ..........................................................................................................728
27.8.7 Flash error response operation ......................................................................................728
27.8.8 Bank0 page read buffers and prefetch operation ..........................................................728
27.8.9 Bank1 Temporary Holding Register .............................................................................730
27.8.10 Read-while-write functionality .....................................................................................731
27.8.11 Wait-state emulation .....................................................................................................732
Chapter 28
Static RAM (SRAM)
28.1 Introduction ...................................................................................................................................735
28.2 Low power configuration ..............................................................................................................735
28.3 Register memory map ...................................................................................................................735
28.4 SRAM ECC mechanism ................................................................................................................735
28.4.1 Access timing ...............................................................................................................736
28.4.2 Reset effects on SRAM accesses ..................................................................................737
28.5 Functional description ...................................................................................................................737
28.6 Initialization and application information .....................................................................................737
Chapter 29
Register Protection
29.1 Introduction ...................................................................................................................................741
29.2 Features .........................................................................................................................................741
MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 15
29.3 Modes of operation ........................................................................................................................742
29.4 External signal description ............................................................................................................742
29.5 Memory map and register description ...........................................................................................742
29.5.1 Memory map ................................................................................................................743
29.5.2 Register description ......................................................................................................744
29.6 Functional description ...................................................................................................................746
29.6.1 General .........................................................................................................................746
29.6.2 Change lock settings .....................................................................................................746
29.6.3 Access errors ................................................................................................................750
29.7 Reset ..............................................................................................................................................750
29.8 Protected registers .........................................................................................................................750
Chapter 30
Software Watchdog Timer (SWT)
30.1 Overview .......................................................................................................................................755
30.2 Features .........................................................................................................................................755
30.3 Modes of operation ........................................................................................................................755
30.4 External signal description ............................................................................................................756
30.5 Memory map and register description ...........................................................................................756
30.5.1 Memory map ................................................................................................................756
30.5.2 Register description ......................................................................................................757
30.6 Functional description ...................................................................................................................761
Chapter 31
Error Correction Status Module (ECSM)
31.1 Introduction ...................................................................................................................................763
31.2 Overview .......................................................................................................................................763
31.3 Features .........................................................................................................................................763
31.4 Memory map and register description ...........................................................................................763
31.4.1 Memory map ................................................................................................................763
31.4.2 Register description ......................................................................................................764
31.4.3 Register protection ........................................................................................................783
Chapter 32
IEEE 1149.1 Test Access Port Controller (JTAGC)
32.1 Introduction ...................................................................................................................................787
32.2 Block diagram ...............................................................................................................................787
32.3 Overview .......................................................................................................................................787
32.4 Features .........................................................................................................................................788
32.5 Modes of operation ........................................................................................................................788
32.5.1 Reset .............................................................................................................................788
32.5.2 IEEE 1149.1-2001 defined test modes .........................................................................788
32.6 External signal description ............................................................................................................789
32.7 Memory map and register description ...........................................................................................790
32.7.1 Instruction Register ......................................................................................................790
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