DS90UB940-Q1: FPD-LinkIII至CSI-2解串器技术详情

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"TI-DS90UB940-Q1.pdf" 是一款由德州仪器(TI)生产的FPD-Link解串器芯片，适用于视频传输应用，如高清多媒体接口(HDMI)或DisplayPort(DP++)。这款解串器芯片能够将FPD-LinkIII的串行信号转换为MIPI CSI-2并行信号，用于连接应用处理器或移动设备/图形处理器。该器件的主要特点包括： 1. 支持高像素时钟频率：高达170MHz，这使得它能处理WUXGA（1920x1200）和1080p60分辨率的视频流，同时支持24位色深，确保了高质量的图像输出。 2. FPD-LinkIII接口：采用单通道或双通道设计，具备偏移补偿能力，提高了信号传输的稳定性和可靠性。 3. MIPID-PHY/CSI-2发送器：提供2通道或4通道的可选操作CSI-2输出端口，适应不同的系统需求。 4. 多通道高速数据传输：每个CSI-2端口最多可支持4个数据通道，每个通道的数据速率可达1.3Gbps，确保高速视频数据的高效传输。 5. 视频格式兼容性：支持多种视频格式，包括RGB888/666/565、YUV422/420以及RAW8，广泛覆盖了常见的视频编码类型。此外，DS90UB940-Q1还集成了一些辅助功能，如热插拔检测(HPD)、显示数据通道/DDC和消费电子控制/CEC，方便系统管理和控制。HS_GPIO (SPI) 提供了灵活的系统接口，可以进行串行通信。I2C接口允许与系统中的其他组件进行通信，而1.8V和3.3V的VDDIO电源选项则提供了电源管理的灵活性。在硬件设计中，DS90UB940-Q1通常与DS90UB949-Q1 serializer（串行器）配对使用，形成完整的视频传输解决方案。产品目录中提供的样片和购买信息、技术文档、工具和软件支持以及社区资源，有助于开发者和工程师在实际项目中集成和使用这款解串器芯片。请注意，TI在数据表中特别指出，此产品数据适用于生产用途，对于安全关键应用，用户需自行评估并确认其适用性。同时，数据表中还包括关于知识产权、免责声明和其他重要信息的注意事项。对于英文版数据表，完整的技术规格可在SNLS479文档中找到。

DS90UB940-Q1

ZHCSEN9A –NOVEMBER 2014–REVISED JANUARY 2016

www.ti.com.cn

(1) Parameter is specified by bench characterization and is not tested in production.

7.8 Timing Requirements for the Serial Control Bus

Over I

C supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SCL

SCL Clock Frequency Standard Mode >0 100 kHz

Fast Mode >0 400 kHz

Fast Plus Mode >0 1 MHz

LOW

SCL Low Period Standard Mode 4.7 µs

Fast Mode 1.3 µs

Fast Plus Mode 0.5 µs

HIGH

SCL High Period Standard Mode 4.0 µs

Fast Mode 0.6 µs

Fast Plus Mode 0.26 µs

HD;STA

Hold time for a start or a

repeated start condition

Figure 8

Standard Mode 4.0 µs

Fast Mode 0.6 µs

Fast Plus Mode 0.26 µs

SU;STA

Set Up time for a start or a

repeated start condition

Figure 8

Standard Mode 4.7 µs

Fast Mode 0.6 µs

Fast Plus Mode 0.26 µs

HD;DAT

Data Hold Time

Figure 8

Standard Mode 0 µs

Fast Mode 0 µs

Fast Plus Mode 0 µs

SU;DAT

Data Set Up Time

Figure 8

Standard Mode 250 ns

Fast Mode 100 ns

Fast Plus Mode 50 ns

SU;STO

Set Up Time for STOP

Condition

Figure 8

Standard Mode 4.0 µs

Fast Mode 0.6 µs

Fast Plus Mode 0.26 µs

BUF

Bus Free Time

Between STOP and START

Figure 8

Standard Mode 4.7 µs

Fast Mode 1.3 µs

Fast Plus Mode 0.5 µs

SCL & SDA Rise Time,

Figure 8

Standard Mode 1000

(1)

Fast Mode 300

(1)

Fast Plus Mode 120

(1)

SCL & SDA Fall Time,

Figure 8

Standard Mode 300

(1)

Fast mode 300

(1)

Fast Plus Mode 120

(1)

Capacitive Load for Each Bus

Line

Standard Mode 400 pF

Fast Mode 400 pF

Fast Plus Mode 550 pF

Input Filter Fast Mode 50 ns

Fast Plus Mode 50 ns

DS90UB940-Q1

www.ti.com.cn

ZHCSEN9A –NOVEMBER 2014–REVISED JANUARY 2016

(1) Specification is ensured by design and is not tested in production.

(2) This parameter is specified by characterization and is not tested in production.

(3) C

LOAD

includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be

<10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2ns delay.

7.9 Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT

HSTX DRIVER

HSTX

DBR

Data bit rate

(1)

MIPI 2 Lanes CSI0_D0±

CSI0_D1±

CSI0_D2±

CSI0_D3±

CSI1_D0±

CSI1_D1±

CSI1_D2±

CSI1_D3±

CSI0_CLK±

CSI1_CLK±

350 1344

Mbps

MIPI 4 Lanes 175 1190

fCLK DDR Clock frequency

(1)

MIPI 2 Lanes 175 672

MHz

MIPI 4 Lanes 87.5 595

ΔV

CMTX(HF)

Common mode voltage

variations HF

(1)

Above 450MHz

15 mV

RMS

ΔV

CMTX(LF)

Common mode voltage

variations LF

(1)

Between 50 and 450MHz

25 mV

RMS

RHS

FHS

20% to 80% Rise and Fall HS

(1)

HS bit rates ≤ 1 Gbps (UI ≥ 1 ns) 0.3 UI

HS bit rates > 1 Gbps (UI < 1 ns) 0.35 UI

Applicable for all HS bit rates.

However, to avoid excessive

radiation, bit rates ≤ 1 Gbps (UI

≥ 1 ns), should not use values

below 150 ps

100 ps

SDD

TX differential return loss

(1)

LPMAX

-18 dB

MAX

-9 dB

LPTX DRIVER

RLP

Rise Time LP

(2) (3)

15% to 85% rise time CSI0_D0±

CSI0_D1±

CSI0_D2±

CSI0_D3±

CSI1_D0±

CSI1_D1±

CSI1_D2±

CSI1_D3±

CSI0_CLK±

CSI1_CLK±

25 ns

FLP

Fall Time LP

(2) (3)

15% to 85% fall time 25 ns

REOT

Rise Time Post-EoT

(1) (3)

30%-85% rise time 35 ns

LP-PULSE-TX

Pulse width of the LP exclusive-

OR clock

(1) (3)

First LP exclusive-OR clock

pulse after Stop state or last

pulse before Stop state

40 ns

All other pulses 20 ns

LP-PER-TX

Period of the LP exclusive-OR

clock

(1)

90 ns

DV/DtSR Slew rate

(2) (3)

Cload = 0pF 500 mV/ns

Cload = 5pF 300 mV/ns

Cload = 20pF 250 mV/ns

Cload = 70pF 150 mV/ns

Cload = 0 to 70pF (Falling Edge

Only)

30 mV/ns

Cload = 0 to 70pF (Rising Edge

Only)

30 mV/ns

Cload = 0 to 70pF (Rising Edge

Only)

30 -

0.075*(V

O,INST -

700)

mV/ns

LOAD

Load capacitance

(3)

0 70 pF

DS90UB940-Q1

ZHCSEN9A –NOVEMBER 2014–REVISED JANUARY 2016

www.ti.com.cn

Switching Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT

(4) (a) 1280x720p60; PCLK = 74.25MHz; 4 MIPI lanes reg0x6c=0x02; reg0x6d=0x84

(b) 1280x720p60; PCLK = 74.25MHz; 2 MIPI lanes reg0x6c=0x02; reg0x6d=0x89

(d) 640x480p60; PCLK = 25MHz; 2 MIPI lanes reg0x6c=0x02; reg0x6d=0x83

(e) Other video formats may require additional register configuration.

DATA-CLOCK TIMING SPECIFICATIONS

(1)

(Figure 10)

INST

UI instantaneous fCLK = CSI-2 DDR Clock

frequency

CSI0_D0±

CSI0_D1±

CSI0_D2±

CSI0_D3±

CSI1_D0±

CSI1_D1±

CSI1_D2±

CSI1_D3±

CSI0_CLK±

CSI1_CLK±

1/(fCLK

* 2)

ΔUI UI variation

PCLK = 25 - 96MHz

UI ≥ 1ns -10% 10% UI

UI < 1ns -5% 5% UI

SKEW(TX)

Data to Clock Skew (measured

at transmitter)

Skew between clock and data

from ideal center

Data rate ≤ 1 Gbps -0.15 0.15 UI

INST

Data rate > 1 Gbps

-0.2 0.2 UI

INST

CSI-2 TIMING SPECIFICATIONS

(1)

(Figure 11, Figure 12)

CLK-MISS

Timeout for receiver to detect

absence of Clock transitions and

disable the Clock Lane HS-RX

CSI0_D0±

CSI0_D1±

CSI0_D2±

CSI0_D3±

CSI1_D0±

CSI1_D1±

CSI1_D2±

CSI1_D3±

CSI0_CLK±

CSI1_CLK±

60 ns

CLK-POST

HS exit 60 +

52*UI

CLK-PRE

Time HS clock shall be driver

prior to any associated Data

Lane beginning the transition

from LP to HS mode

8 UI

CLK-

PREPARE

Clock Lane HS Entry

38 95 ns

CLK-SETTLE

Time interval during which the

HS receiver shall ignore any

Clock Lane HS transitions

95 300 ns

CLK-TERM-EN

Time-out at Clock Lane Display

Module to enable HS

Termination

Time for

Dn to

reach

VTERM-

38 ns

CLK-TRAIL

Time that the transmitter drives

the HS-0 state after the last

payload clock bit of a HS

transmission burst

60 ns

CLK-

PREPARE

CLK-ZERO

TCLK-PREPARE + time that the

transmitter drives the HS-0 state

prior to starting the Clock

300 ns

D-TERM-EN

Time for the Data Lane receiver

to enable the HS line termination

Time for

Dn to

reach V-

TERM-

35 +

4*UI

EOT

Transmitted time interval from

the start of t

HS-TRAIL

to the start

of the LP-11 state following a HS

burst

see

(4)

105 +

12*UI

HS-EXIT

Time that the transmitter drives

LP=11 following a HS burst

100 ns

HS-PREPARE

Data Lane HS Entry 40 +

4*UI

85 +

6*UI

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