"2022年10月IJSCBC特刊：2021亚洲固态电路会议专题介绍"

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The October 2022 issue of the International Journal of Solid-State Circuits and Components (IJSCBC) features a special section on the 2021 Asian Solid-State Circuits Conference (A-SSCC), showcasing cutting-edge research and advancements in the field of solid-state circuits. The special section kicks off with an introduction by J.-H. Choi, P.-C. Huang, S. Yin, and W. Rhee, highlighting the importance of the A-SSCC and setting the stage for the following papers. One of the featured papers in this special section presents an on-chip relaxation oscillator implemented in a 5-nm FinFET technology using a frequency-error feedback loop. This innovative design leverages the advanced capabilities of FinFET technology to achieve high precision and stability in oscillator performance. The paper demonstrates the potential of on-chip relaxation oscillators for a wide range of applications, from timing generation to sensor interfacing. In addition to the on-chip relaxation oscillator, the special section includes a diverse range of papers covering various topics in solid-state circuit design and implementation. These papers explore new techniques for power-efficient circuit design, advanced modeling and simulation methods, novel circuit architectures, and emerging applications of solid-state circuits in areas such as healthcare, communications, and artificial intelligence. Overall, the special section on the 2021 A-SSCC in the October 2022 issue of IJSCBC provides a comprehensive overview of the latest research and developments in solid-state circuit design and implementation. The contributions from researchers and practitioners in the field demonstrate the ongoing advancements and innovation in solid-state circuits, paving the way for future breakthroughs in technology and applications.

2906 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 10, OCTOBER 2022

Fig. 12. (a) Measured frequency variations with bias current from four chip samples. (b) Variation in nominal frequency of 77 MHz due to process when

measured from 16 samples. (c) Power breakdown of the oscillator.

TABLE I

ERFORMANCE SUMMARY AND COMPARIS ON WITH STA TE-OF-THE-ART OSCILLATORS

signiﬁcantly reduce the oscillator’s sensitivity to temperature

variations. Further improvement in thermal stability can be

achieved by adding a TC-DAC to I

REF

branch in Fig. 7(b).

This enables α

and α

in (8) to match well and eliminates

even the ﬁrst-order d ependency visible in Fig. 11(c).

Fig. 12(a) shows the sensitivity of the oscillator to the bias

current, I

bias

, with and without the FEF loop. The comparator

delay changes with I

bias

, and so does f

osc

.However,when

the FEF loop is enabled, the sensitivity to I

bias

is reduced

from ∼13% to <0.7%, further conﬁrming the effectiveness of

the FEF loop. The comparator bias current is switched to an

ON-chip tunable current source using an analog mux as shown

in Fig. 7(b). The oscillation frequency at 30

◦

C and 1.2-V

supply is 77 MHz. However, the impact of process variations

in the ﬁne geometry technologies, such as 5-nm FinFET,

is signiﬁcant [20]. Consequently, as shown in Fig. 12(b),

the nominal frequency varies from a minimum of 72.9 to

82.1 MHz over 16 samples from four different wafers. The

primary source of the frequency spread with the process is

the var iation in I

REF

which stems from the mismatch in PNP

BJTs. In ﬁne geometry processes, the BJTs have a low current

gain which increases the process spread in V

. Besides, the

BJTs have a larger spread in non-ideality factor and larger

variability in V

due to emitter ﬁn width mismatch in 1:N

BJT pair [Q

and Q

in Fig. 7(b)]. These nonidealities increase

the current source I

REF

for the SS chips in Fig. 12(b) making

them oscillate with higher frequency. The process spread in

osc

can be trimmed by adding a level DAC in Fig. 7(b) also

to I

REF

branch. Fig. 12(c) shows the oscillator’s simulated

power breakdown. The total power consumption of 0.84 mW

is dominated by the bandgap reference (68.5%). In a real

SoC, the bandgap r eference is shared between multiple blocks

ON-chip. Hence, its power consumption will be amortized. The

oscillator core only consumes 31.4% of the total power.

MEHTA et al. : ON-CHIP RELAXATION OSCILLATOR IN 5-nm FinFET 2907

Table I summarizes the performance of the proposed oscil-

lator a nd compares it with previously publishe d state-of-the-art

works. The proposed design operates at 7 7 MHz which is one

of the h ighest among the recently published works. Thanks

to the small feature size of the 5-nm FinFET process, the

proposed oscillator achieves the lowest area even though it

uses a bandgap reference for generating the reference voltage

and reference current sources. Compared with [4], [5], the TIE

jitter is reduced by 3×. While the TIE is comparable to [15],

the thermal stability is 6× better. The frequency variations

with supply and temperature reported in Table I for this design

are the worst case values from 16 and eight chip samples,

respectively.

V. C

ONCLUSION

A relaxation oscillator using a FEF loop is describ ed for

securing SoCs against physical clock attacks. From a security

perspective, the

ON-chip oscillator should achieve good sta-

bility with supply and temperature as well as good TIE jitter

and period jitter. The oscillator using an FEF loop is shown to

meet these requirements using circuit techniques such as CDS-

based error-ampliﬁer, current splitter, and reuse of loop-ﬁlter

as a hold capacitor. Realized in 5-nm FinFET, the 77-MHz

oscillator achieves 11-μW/MHz power efﬁciency and a TIE

of 2.81 ns over 10 K cycles with a period jitter of 60 ps. The

worst case frequency stability over 1 .1–1.35-V supply and the

temperature range of −40

◦

C to 125

◦

Cis±0.25% and ±0.3%,

respectively. This performance combined with the use of no

external components makes the proposed oscillator well-suited

for securing the boot-up process and as a reference for

ON-chip

clock monitors.

CKNOWL EDGMENT

The authors thank Brian Zimmer and Sudhir Kudva for

layout help and Neil Pham for equipment support.

EFERENCES

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[10] N. Mehta, S. Tell, W. Turner, L. Tatro, G. Goh, and C. T. Gray,

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10 K cycles and ±0.3% thermal stability using frequency-error feed-

back loop,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC),

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[11] U. Denier, “Analysis and design of an ultralow-power CMOS relaxation

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[14] J. Jung, I.-H. Kim, S.-J. Kim, Y. Lee, and J.-H. Chun, “A 1.08-nW/kHz

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Nandish Mehta (Senior Member, IEEE) received

the M.Sc. degree in microelectronics from the Delft

Uni versity of T echnology, Delft, The Netherlands,

in 2013, and the Ph.D. degree in electrical engi-

neering and computer science from the University of

California at Berkeley, Berkeley, CA, USA, in 2019.

He held internships with Apple Inc., Cupertino,

CA, USA; Ayar labs, Emeryville, CA, USA; and

Broadcom Inc., Bunnik, The Netherlands. He is

currently with Nvidia Corporation, Santa Clara, CA,

USA. His research focuses on applications of inte-

grated silicon photonics, analog-mixed signal circuits, and serial links.

Dr. Mehta was a recipient of the Foundation for Excellence Scholarship

in 2005, the Intel Scholarship in 2008, the NXP Scholarship in 2011, the

Department of EECS Fellowship in 2014, the ADI Outstanding Student

Designer Award in 2018, and the IEEE SSCS Predoctoral Award in 2019.

2908 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 10, OCTOBER 2022

Stephen G. Tell (Member, IEEE) received the

B.S.E. degree in electrical engineering from Duke

Uni versity, Durham, NC, USA, in 1989, and

the M.S. degree in computer science from the

Univ ersity of North Carolina, Chapel Hill, NC,

in 1991.

He worked on parallel graphics systems and

high-speed signaling as a Senior Research

Associate with UNC/Chapel Hill Chapel Hill,

from 1991 to 1999, and in 1999, he joined Velio,

Inc., Raleigh, NC, to develop circuits and control

systems for high-speed SerDes products. This work continued at Rambus,

Chapel Hill, where he designed the logic for a SerDes with the lowest energy

per bit demonstrated up to that time. He joined Nvidia Corporation, Santa

Clara, CA, USA, in 2009, as a founding member of the Circuits Research

Group, where he works as a Senior Research Scientist. He has been awarded

more than 20 U.S. patents. His current research interests include custom

circuit design and the surrounding test and control logic for intra- and

inter-chip communication.

Walker J. Turner (Member, IEEE) received the

B.S., M.S., and Ph.D. de grees in electrical and

computer engineering from the Uni versity of Florida,

Gainesville, FL, USA, in 2009, 2012, and 2015,

respectively.

In 2014, he worked as a Contractor with the

U.S. Army Research Laboratory, Adelphi, Mary-

land, where he was dev e loping wirelessly pow-

ered systems and integrated low-noise ampliﬁers for

piezoelectric E-ﬁeld sensors. He joined the Circuits

Research Group, NVIDIA, Durham, Durham, NC,

USA, in 2015 where he works on energy-efﬁcient, high-speed signaling

systems for on- and off-chip communication. He also served as a Teach-

ing, Assistant Professor with North Carolina State University, Raleigh, NC,

from 2019 to 2020, where he instructed an undergraduate micro-electronics

engineering course. He is currently a Senior Research Scientist with NVIDIA

Corporation, Santa Clara, CA, USA.

Lamar Tatro received the B.S. degree in electrical

engineering and computer science from the Univer-

sity of California at Berkeley, Berkeley , CA, USA.

He is currently in mixed-signal design v alidation

with Nvidia Corporation, Santa Clara, CA, where he

is responsible for high-speed transcei ver validation.

He has over 20 years of experience in transceiver

and mixed-signal validation. His current research

interests are high-speed signaling and emerging I/O

solutions.

Jih-Ren Goh received the M.Sc. degree in electrical

engineering from National Cheng Kung University,

Tainan City, Taiwan, in 2014.

He is currently with Nvidia Corporation, Santa

Clara, CA, USA, where he is working on MIPI

display interface and mixed-signal circuit design.

His research focus is on mixed-signal circuit design

and high-speed SERDES.

C. Thomas Gray (Senior Member, IEEE) received

the B.S. degree in computer science and mathe-

matics from the Mississippi College, Clinton, MS,

USA, and the M.S. and Ph.D. degrees in computer

engineering from North Carolina State Uni versity,

Raleigh, NC, USA.

From 1993 to 1998, he was an Advisory Engineer

with IBM, Research Triangle Park, NC, where he

was working in transceiver design for communica-

tion systems. From 1998 to 2004, he was a Senior

Staff Design Engineer with the Analog/Mixed Signal

Design Group, Cadence Design Systems, Cary, NC, where he was working

on SerDes system architecture. From 2004 to 2010, he was a Consultant

Design Engineer with Artisan/ARM, Cary, and the T echnical Lead of SerDes

architecture and design. In 2010, he joined Nethra Imaging, Cary, as a System

Architect. His work experience includes digital signal processing design

and CMOS implementation of DSP blocks, as well as high-speed serial-

link communication systems, architectures, and implementation. In 2011,

he joined NVIDIA, Durham, NC, where he is currently the Senior Director of

circuits research leading activities related to high-speed signaling, low-energy,

and resilient memories, circuits for machine learning, and variation tolerant

clocking and power delivery.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 10, OCTOBER 2022 2909

A BJT-Based Temperature-to-Frequency Converter

With ±1

◦

C(3σ) Inaccuracy From −40

◦

Cto

140

◦

C for On-Chip Thermal Monitoring

Jee-Ho Park , Graduate S tudent Member, IEEE, Jung-Hye Hwang, Graduate Student Member, IEEE,

Changyong Shin, and Seong-Jin Kim

, Senior Member, IEEE

Abstract—This article presents a bipolar junction transistor

(BJT)-based CMOS temperature-to-frequency converter (TFC).

A relaxation oscillator (ROSC) consisting of an integrating capac-

itor, a current source, and a comparator converts the ratio of the

complementary-to-absolute-temperature (CTAT) voltage to the

proportional-to-absolute-temperature (PTAT) voltage created by

the BJT core to frequency. To improve the temperature accuracy,

we incorporate a capacitor ﬂipping technique to remove an offset

of the comparator and a settling time error when resetting the

integrating capacitor. Moreover, bootstrapped NMOS switches

with the triple well structure are implemented to suppress leakage

current and prevent from forming parasitic BJTs when the

negative CTAT is applied to them by the proposed ﬂipping

technique. The prototype fabricated in a 0.11-μm CMOS process

consumes 3.1-μW power and occupies a 0.025-mm

active area.

Measurements of 18 samples with the digital trimming show an

inaccuracy of ±1

◦

C(3σ) from −40

◦

C to 140

◦

C. The area- and

energy-efﬁcient TFC is applicable to monitor the temperature

inside integrated chips.

Index Terms— Bipolar junction transistor (BJT), CMOS tem-

perature sensor, ﬂipping technique, low power consumption,

relaxation oscillator (ROSC), small active area, temperature-to-

frequency converter (TFC).

I. INTRODUCTION

EMPERATURE sensors are widely used in various

ﬁelds including on-chip thermal management [1]–[3],

the Internet of Things [4], and image sensors [5]. To ade-

quately compensate for the process-dependent parameters

within the temperature range of its app lications, the temper-

ature sensor should detect the temperature locally. Therefore,

Manuscript receiv e d 20 January 2022; revised 29 March 2022 and 1 June

2022; accepted 8 June 2022. Date of publication 21 June 2022; date of

current version 26 September 2022. This article was approved by Associate

Editor Po-Chiun Huang. This work was supported in part by the Institute of

Information and Communications Technology Planning and Evaluation (IITP)

Grant funded by the Korea Gove rnment (MSIT) through the project Devel-

opment of 5G-Based 3D Spatial Scanning Device Technology for Virtual

Space Composition under Grant 2020-0-00103 and in part by the Korea

Institute for Advancement of Technology (KIAT) Grant funded by the Korea

Gove rnment (MOTIE) through HRD Program for Industrial Innovation under

Grant P0017011. (Corresponding author: Seong-Jin Kim.)

Jee-Ho Park, Jung-Hye Hwang, and Seong-Jin Kim are with the Department

of Electrical Engineering, Ulsan National Institute of Science and Technology,

Ulsan 44919, South Korea (e-mail: kimsj@unist.ac.kr).

Changyong Shin was with the Department of Electrical Engineering, Ulsan

National Institute of Science and Technology, Ulsan 44919, South Korea.

He is now with Anapass, Seoul 08375, South Korea.

Color versions of one or more ﬁgures in this article are available at

https://doi.org/10.1109/JSSC.2022.3182708.

Digital Object Identiﬁer 10.1109/JSSC.2022.3182708

a temperature-sensing core needs to occupy a small active

area for placing next to the sensing part with a reasonable

temperature accuracy. Also, a highly energy-efﬁcient core with

low pow er consumption is desirab le to mon itor temperature

being changed slowly and continuously without a signiﬁcant

increase in the total power consumption of the chip. The

bipolar junc tion transistor (BJT) is one of the attractive devices

for temperature sensing of the chip because it offers relatively

high accuracy with a wide temperature range and long-term

operation stability compared with other resistor or MOSFET-

based temperature sensors. Moreover, the BJT-based tempera-

ture sensor readily shares the circuit component with a voltage

reference block which is inevitable for the chip [6].

The conventional BJT-based temperature sensors com-

pare a bandgap reference voltage which is independent

on temperature with a reinforced proportional-to-absolute-

temperature (PTAT) voltage from two complementary-to-

absolute-temperature (CTAT) voltages g enerated by two BJTs

with different cu rrent densities, thus estimating the tem -

perature [7], [8]. They incorporate various calibration and

trimming techniques to suppress temperature-sensing errors

mainly stemming from pro cess spread on the CTAT voltage

[9]. An on-chip modulated trimming in the analog domain

improves the temperature accuracy as high as ±0.1

◦

C with

the overhead on the area and power consumption. In contrast,

an alternative calibration in an off-chip digital domain offers

a comparable accuracy of ±0.15

◦

C without the complex-

ity of the analog circuitry [10], [11]. A gain factor of the

PTAT voltage for the bandgap reference is easily adjusted to

mitigate the process variation. The charge-balancing sigma-

delta (SD) modulators with on- or off-chip calibration schemes

are predominantly adopted to the temperature sensors to deal

with the CTAT and PTAT voltages. They achieve excel-

lent temperature accuracy but o ccupy a relatively large area

and require a decimation ﬁlter, which may not be desir-

able for monitoring the temperature of smart sensors or

system-on-chips.

Recently, a time-domain temperature conversion scheme

employing a simple relaxation oscillator (ROSC) and achiev-

ing a moderate temperature accuracy has emerg ed to relax

the area and power requirements of the analog front-end

(AFE) [12]–[18]. Instead of converting the CTAT and PTAT

voltages to digital values, these temperature sensors modulate

temperature information to a duty cycle in the time domain.

See https://www.ieee.org/publications/rights/index.html for more information.

2910 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 10, OCTOBER 2022

Fig. 1. Time-domain-based temperature sensor: (a) simpliﬁed schematic utilizing the CTAT and PTAT current with a hysteresis comparator and (b) simpliﬁed

schematic with a duty-cycling modulator.

Fig. 1(a) shows a simpliﬁed schematic of the time-domain

temperature sensor [ 14]. The PTAT and CTAT currents gener-

ated from the BJT core are integrated into the capacitor with

different gains at each phase. The duty ratio of the charging

and discharging is insensitive to the voltage references, V

and

, making the AFE simple [14], [15]. However, an additional

ampliﬁer is necessary to generate the CTAT current from

the BJT core, and the current gains are determined by the

analog components which require accurate trimming circuits

in the analog domain. Also, it is necessary to measure both

charging and discharging periods precisely by other building

blocks. Another time-domain conversion scheme is shown

in Fig. 1(b) [16]. The temperature information is modulated

into the duty-cycle-modulated oscillation output that occurs by

comparin g the PTAT and CTAT voltages with a ramp voltage,

, created by a reference current source and a capacitor.

The analog circuit complexity is alleviated because the gain is

controlled in the digital domain. However, it still suffers from

accurate measurements of both phase durations for estimating

temperature.

This article presents a BJT-based temperature-to -frequency

conver ter (TFC) that requires measuring on ly the oscillation

frequency for detecting temperature. In addition, a ﬂipping

technique is introduced to mitigate the non-idealities of the

proposed TFC [18]. The prototype achieves 3.1-μWpower

consumption and a small occupying area of 0.025 mm

including the BJT core and the analog and digital blocks in

a 0.11-μm CMOS p rocess with an inaccuracy of ±1

◦

C(3σ)

from −40

◦

C to 140

◦

C. The r est of this article is organized as

follows. Section II describes the operation of the TFC and dis-

cusses the main error sources followed by the proposed error

resolving techniques. Section III discusses the detailed circuit

implementation o f the proposed TFC. Section IV presents the

experimental results. Finally, Section V concludes this article.

II. T

EMPERATURE-TO -FREQUENCY CONVE RTER

A. Operating Principle of the Proposed TFC

Fig. 2 shows the simpliﬁed circuit diagram of the proposed

TFC. It consists of an integration capacitor, C

INT

,aPTAT

current source, I

PTAT

, a CTAT reference voltage, V

CTAT

from

the BJT core, and a comparator. The C

INT

is being charged up

Fig. 2. Simpliﬁed circuit diagram of the proposed architecture.

by the I

PTAT

until the C

INT

voltage, V

, reaches the CTAT

voltage which is a base–emitter voltage, V

. After that,

the comparator is toggled, and the V

is reset. Then, the

charging process is repeated to generate a constant oscillation

as depicted with the blue line in the timing diagram. After

passing a digital ﬂip-ﬂop, its waveform becomes a square pulse

having a constant oscillation period with a 50% duty cycle.

Since the I

PTAT

is proportional to the PTAT voltage, V

PTAT

half of the oscillation period (t

) is expressed as

= RC

INT

CTAT

PTAT

(1)

where R is the resistance generating the I

PTAT

from the

PTAT

at the BJT core. In other words, its frequency, which

is the reciprocal value of the period, is proportional to the

temperature. In particular, the frequency is given by the ratio

of V

to V

, which can be readily linearized by a digital

calibration with the adjustment of the coefﬁcient, α,asshown

in Fig. 3. The ﬁnal linear function of temperature, μ,isgiven

μ =

+ α

INT

CTAT

PTAT

+ α

. (2)

The μ can be translated to temperature with the Celsius unit

by a linear ﬁtting as follows:

T = A · μ − B (3)

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