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首页EFR32FG1:低功耗物联网专用协议芯片数据手册
EFR32FG1:低功耗物联网专用协议芯片数据手册
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更新于2024-07-17
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EFR32FG1是一款由Silicon Labs公司推出的专为物联网(IoT)设备设计的嵌入式系统-on-Chip(SoC)芯片。该芯片隶属于Wireless Gecko家族,其FlexGeo协议系列是其核心组成部分,专注于提供高效能、低功耗的专用协议网络解决方案。FlexGeo SoC的优势在于其高度集成的设计,旨在简化开发过程并优化能源利用。 这款SoC的核心是一颗32位的ARM Cortex-M4处理器,最高工作频率可达40 MHz,确保了出色的计算性能。它提供了灵活的内存和无线通信配置选项,支持多种封装形式,如QFN,以适应不同尺寸的应用场景和需求。 FlexGeo的一个关键特性是其12通道的外围设备 Reflex System,这使得微控制器(MCU)的外设能够实现自主交互,提升了系统的灵活性和响应速度。此外,它还集成了硬件加密加速器和随机数生成器,增强了数据安全性和保密性。 通信方面,EFR32FG1内置了集成平衡器,适用于2.4 GHz频段,并配备了功率放大器,可提供高达19.5 dBm的2.4 GHz发射功率和20 dBm的Sub-GHz频段发射功率,确保了远距离无线通信的能力。集成的直流-直流转换器还具有噪声抑制功能,有助于提升信号质量。 应用领域广泛,包括但不限于家庭和建筑自动化与安全系统、计量设备、电子货架标签、工业自动化、商业和零售照明等。这些应用都依赖于EFR32FG1的高效能、低功耗特性和丰富的功能集,使其成为物联网设备的理想选择,特别是在需要长时间运行且对能耗敏感的场景中。EFR32FG1以其卓越的技术性能和广泛的适用性,正在推动着物联网设备向更加智能、节能的方向发展。
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3.9.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of
sources, including pins configurable as either single-ended or differential.
3.9.4 Digital to Analog Current Converter (IDAC)
The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin
or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with
several ranges consisting of various step sizes.
3.10 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFR32FG1. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.11 Core and Memory
3.11.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• Up to 256 kB flash program memory
• Up to 32 kB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface
3.11.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-
ergy modes EM0 Active and EM1 Sleep.
3.11.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller features 8 channels capable of performing memory operations independently of
software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and stag-
ed, enabling sophisticated operations to be implemented.
EFR32FG1 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.1 | 11
![](https://csdnimg.cn/release/download_crawler_static/11607626/bg11.jpg)
3.12 Memory Map
The EFR32FG1 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFR32FG1 Memory Map — Core Peripherals and Code Space
EFR32FG1 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.1 | 12
![](https://csdnimg.cn/release/download_crawler_static/11607626/bg12.jpg)
Figure 3.3. EFR32FG1 Memory Map — Peripherals
3.13 Configuration Summary
The features of the EFR32FG1 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
Table 3.1. Configuration Summary
Module Configuration Pin Connections
USART0 IrDA SmartCard US0_TX, US0_RX, US0_CLK, US0_CS
USART1
IrDA I
2
S SmartCard
US1_TX, US1_RX, US1_CLK, US1_CS
TIMER0 with DTI. TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 TIM1_CC[3:0]
EFR32FG1 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.1 | 13
![](https://csdnimg.cn/release/download_crawler_static/11607626/bg13.jpg)
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on T
AMB
=25 °C and V
DD
= 3.3 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Refer to Table 4.2 General Operating Conditions on page 17 for more details about operational supply and temperature limits.
EFR32FG1 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 14
![](https://csdnimg.cn/release/download_crawler_static/11607626/bg14.jpg)
4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-
bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter Symbol Test Condition Min Typ Max Unit
Storage temperature range T
STG
-50 — 150 °C
External main supply voltage V
DDMAX
0 — 3.8 V
External main supply voltage
ramp rate
V
DDRAMPMAX
— — 1 V / μs
Voltage on any 5V tolerant
GPIO pin
1
V
DIGPIN
-0.3 — Min of 5.25
and IOVDD
+2
V
Voltage on non-5V tolerant
GPIO pins
-0.3 — IOVDD+0.3 V
Voltage on HFXO pins V
HFXOPIN
-0.3 — 1.4 V
Input RF level on pins
2G4RF_IOP and
2G4RF_ION
P
RFMAX2G4
— — 10 dBm
Voltage differential between
RF pins (2G4RF_IOP -
2G4RF_ION)
V
MAXDIFF2G4
-50 — 50 mV
Absolute Voltage on RF pins
2G4RF_IOP and
2G4RF_ION
V
MAX2G4
-0.3 — 3.3 V
Input RF level on pins
SUBGRF_IP and
SUBGRF_IN
P
RFMAXSUBG
— — 10 dBm
Voltage differential between
RF pins (SUBGRF_IP -
SUBGRF_IN)
V
MAXDIFFSUBG
-50 — 50 mV
Absolute Voltage on RF pins
SUBGRF_IP, SUBGRF_IN,
SUBGRF_OP, and
SUBGRF_ON
V
MAXSUBG
-0.3 — 3.3 V
Total current into VDD power
lines (source)
I
VDDMAX
— — 200 mA
Total current into VSS
ground lines (sink)
I
VSSMAX
— — 200 mA
Current per I/O pin (sink) I
IOMAX
— — 50 mA
Current per I/O pin (source) — — 50 mA
Current for all I/O pins (sink) I
IOALLMAX
— — 200 mA
Current for all I/O pins
(source)
— — 200 mA
Voltage difference between
AVDD and VREGVDD
ΔV
DD
— — 0.3 V
EFR32FG1 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 15
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