"TI LIN2029-Q1收发器及控制器详解"
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The TI-TLIN2029-Q1.pdf document provides information about the Lin收发器 (LIN Transceiver) from Texas Instruments. This Lin Transceiver is a LIN controller or SCI/UART designed for use in automotive applications. It operates with a VDD power supply and features an I/O interface for communication with a microcontroller. The device supports both receive (RX) and transmit (TX) functions, and does not have built-in pullup resistors.
The Lin Transceiver is connected to a LIN bus, which can be used for communication between different nodes in a LIN network. It has a pullup resistor with a value of 1k ohm and a capacitor of 220 pF for bus signal filtering. The device also has a VBAT pin for battery voltage monitoring and a VDD pin for power supply connection.
The Lin Transceiver is suitable for use as a LIN bus master node in automotive systems. It has a low-power design and can be operated with a voltage supply ranging from 5V to 27V. The device is equipped with built-in protection features, such as overvoltage and reverse polarity protection, to ensure reliable operation in harsh automotive environments.
In conclusion, the Lin Transceiver from Texas Instruments is a high-quality and reliable solution for automotive LIN communication applications. With its advanced features and robust design, it meets the demanding requirements of modern automotive systems.
8
TLIN2029-Q1
ZHCSH95B –OCTOBER 2017–REVISED FEBRUARY 2018
www.ti.com.cn
Copyright © 2017–2018, Texas Instruments Incorporated
(1) Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are
defined for 10.4-kbps operation. The TLIN1029 also meets these lower data rate requirements, while it is capable of the higher speed
20-kbps operation as specified by duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle
definitions, for details see the SAEJ2602 specification
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
D1
12V
Duty Cycle 1 (ISO/DIS 17987 Param
27)
(1)
TH
REC(MAX)
= 0.744 x V
SUP
, TH
DOM(MAX)
= 0.581 x V
SUP
, V
SUP
= 7 V to 18 V, t
BIT
= 50 µs (20 kbps), D1 = t
BUS_rec(min)
/(2 x
t
BIT
) (See 图 18, 图 19)
0.396
D1
12V
Duty Cycle 1
TH
REC(MAX)
= 0.625 x V
SUP
, TH
DOM(MAX)
= 0.581 x V
SUP
, V
SUP
= 4 V to 7 V, t
BIT
=
50 µs (20 kbps), D1 = t
BUS_rec(min)
/(2 x
t
BIT
) (See 图 18, 图 19)
0.396
D2
12V
Duty Cycle 2 (ISO/DIS 17987 Param 28)
TH
REC(MAX)
= 0.422 x V
SUP
, TH
DOM(MIN)
= 0.284 x V
SUP
, V
SUP
= 4.6 V to 18 V,
t
BIT
= 50 µs (20 kbps), D2 =
t
BUS_rec(MAX)
/(2 x t
BIT
) (See 图 18, 图 19)
0.581
D3
12V
Duty Cycle 3 (ISO/DIS 17987 Param 29)
TH
REC(MAX)
= 0.778 x V
SUP
, TH
DOM(MAX)
= 0.616 x V
SUP
, V
SUP
= 7 V to 18 V, t
BIT
= 96 µs (10.4 kbps), D3 = t
BUS_rec(min)
/(2
x t
BIT
) (See 图 18, 图 19)
0.417
D3
12V
Duty Cycle
TH
REC(MAX)
= 0.645 x V
SUP
, TH
DOM(MAX)
= 0.616 x V
SUP
, V
SUP
= 4 V to 7 V, t
BIT
=
96 µs (10.4 kbps), D3 = t
BUS_rec(min)
/(2 x
t
BIT
) (See 图 18, 图 19)
0.417
D4
12V
Duty Cycle 4 (ISO/DIS 17987 Param 30)
TH
REC(MIN)
= 0.389 x V
SUP
, TH
DOM(MIN)
=
0.251 x V
SUP
, V
SUP
= 4.6 V to 18 V, t
BIT
= 96 µs (10.4 kbps), D4 = t
BUS_rec(MAX)
/(2
x t
BIT
) (See 图 18, 图 19)
0.59
D1
24V
Duty Cycle 1 (ISO/DIS 17987 Param
72)
(1)
TH
REC(MAX)
= 0.710 x V
SUP
, TH
DOM(MAX)
= 0.544 x V
SUP
, V
SUP
= 15 V to 36 V, t
BIT
= 50 µs (20 kbps), D1 = t
BUS_rec(min)
/(2 x
t
BIT
) (See 图 18, 图 19)
0.33
D2
24V
Duty Cycle 2 (ISO/DIS 17987 Param 73)
TH
REC(MAX)
= 0.446 x V
SUP
, TH
DOM(MIN)
= 0.302 x V
SUP
, V
SUP
= 15.6 V to 36 V,
t
BIT
= 50 µs (20 kbps), D2 =
t
BUS_rec(MAX)
/(2 x t
BIT
) (See 图 18, 图 19)
0.642
D3
24V
Duty Cycle 3 (ISO/DIS 17987 Param 74)
TH
REC(MAX)
= 0.744 x V
SUP
, TH
DOM(MAX)
= 0.581 x V
SUP
, V
SUP
= 7 V to 36 V, t
BIT
= 96 µs (10.4 kbps), D3 = t
BUS_rec(min)
/(2
x t
BIT
) (See 图 18, 图 19)
0.386
D3
24V
Duty Cycle
TH
REC(MAX)
= 0.645 x V
SUP
, TH
DOM(MAX)
= 0.581 x V
SUP
, V
SUP
= 4 V to 7 V, t
BIT
=
96 µs (10.4 kbps), D3 = t
BUS_rec(min)
/(2 x
t
BIT
) (See 图 18, 图 19)
0.386
D4
24V
Duty Cycle 4 (ISO/DIS 17987 Param 75)
TH
REC(MIN)
= 0.442 x V
SUP
, TH
DOM(MIN)
=
0.284 x V
SUP
, V
SUP
= 4.6 V to 36 V, t
BIT
= 96 µs (10.4 kbps), D4 = t
BUS_rec(MAX)
/(2
x t
BIT
) (See 图 18, 图 19)
0.591
7.8 Timing Requirements
SYMBOL DESCRIPTION TEST CONDITIONS MIN NOM MAX UNIT
t
rx_pdr,
t
rx_pdf
Receiver rising propagation delay time
(ISO/DIS 17987 Param 31, 76)
R
RXD
= 2.4 kΩ,
CRX
D = 20 pF (See 图 20
and 图 21 )
6 µs
t
rs_sym
Symmetry of receiver propagation delay
time Receiver rising propagation delay
time
Rising edge with respect to falling edge,
(trx_sym = trx_pdf – trx_pdr),
RRX
D = 2.4
kΩ
, CR
XD = 20 pF (See 图 20 and
图 21 )
–2 2 µs
t
LINBUS
LIN wakeup time (Minimum dominant
time on LIN bus for wakeup)
See 图 24, 图 27, and 图 28) 25 65 150 µs
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