DS90UB947-Q1：1080P LVDS双通道串行器/解串器芯片

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DS90UB947-Q1是一款专为LVDS（低压差分信号）设计的双通道串行器，适用于FPD-LinkIII接口，支持高达1080P的高清视频传输。该器件由德州仪器（TI）制造，主要用于汽车应用，符合AEC-Q100标准，能在-40°C至+105°C的工作温度范围内稳定工作。这款串行器提供2条数据通道，每通道速率可达3Gbps，确保了高速、低延迟的数据传输。其输入端口包括DIN0+、DIN0-、DIN1+、DIN1-等，这些信号用于接收来自图形处理器或显示控制器的并行数据。同时，DS90UB947-Q1还包括一个时钟输入（CLK+/ -）以同步数据传输。 DS90UB947-Q1的主要特点包括： 1. 汽车级认证：该器件满足AEC-Q100 Grade 2的温度等级要求，适合在汽车的苛刻环境中使用。 2. 高分辨率支持：能够支持WUXGA（1920x1200）和1080p60的视频分辨率，提供24位颜色深度，确保高质量的图像输出。 3. 高速传输：每个通道的速率可达3Gbps，总共6Gbps的带宽，确保了高清视频的流畅传输。 4. FPD-LinkIII接口：采用OpenLDI（开放式低压差分接口）标准，提供低功耗、低电磁干扰的解决方案。 5. 串行化功能：将并行数据转换为LVDS串行数据，通过DOUT0+、DOUT0-、DOUT1+、DOUT1-输出。 6. 接口控制：包含SPI（串行外设接口）控制的D_GPIO引脚，可用于配置和控制设备。 7. 电源管理：支持1.8V和3.3V的VDDIO电压，适应不同的系统需求。 8. I2C通信：提供I2C接口，便于与系统中的其他组件进行通信和配置。 9. 完善的文档和技术支持：包括产品手册、技术文档、工具软件以及社区支持，方便用户开发和故障排查。 DS90UB947-Q1是一款高性能、高可靠性的串行器，专为汽车电子领域的高清视频传输而设计。它通过高效的串行化处理，实现了从图形处理器到FPD-LinkIII接口的高效数据传输，是汽车娱乐系统、仪表盘显示器以及其他车载显示应用的理想选择。

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I2C

Interface

I2C

PAT

GEN

Open-LDI

OLDI

Interface

Open LDI

Analog

Regs

Clocks

DFT

Audio

I2S

FPD3 TX

Analog

FPD-Link III

FPD3 TX

Analog

FPD-Link III

FPD-Link III TX

Digital

FPD-Link III TX

Digital

FPD3

Output

Select

Config

Single/Dual

Control

DS90UB947-Q1

SNLS454A –NOVEMBER 2014–REVISED MARCH 2019

www.ti.com

Product Folder Links: DS90UB947-Q1

7 Detailed Description

7.1 Overview

The DS90UB947-Q1 converts a single or dual FPD-Link (Open LDI) interface (up to 8 LVDS lanes + 1 clock) to

an FPD-Link III interface. This device transmits a 35-bit symbol over a single serial pair operating up to 3.36Gbps

line rate, or two serial pairs operating up to 2.975Gbps line rate. The serial stream contains an embedded clock,

video control signals, RGB video data, and audio data. The payload is DC-balanced to enhance signal quality

and support AC coupling.

The DS90UB947-Q1 serializer is intended for use with a DS90UB926Q-Q1, DS90UB928Q-Q1, DS90UB940-Q1,

DS90UB948-Q1 deserializer.

The DS90UB947-Q1 serializer and companion deserializer incorporate an I2C compatible interface. The I2C

compatible interface allows programming of serializer or deserializer devices from a local host controller. In

addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between

serializer/deserializer as well as remote I2C slave devices.

The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward

channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to

serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial

link from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at

either side of the serial link.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 High-Speed Forward Channel Data Transfer

The High-Speed Forward Channel is composed of 35 bits of data containing RGB data, sync signals, I2C,

GPIOs, and I2S audio transmitted from serializer to deserializer. Figure 12 shows the serial stream per clock

cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized,

balanced and scrambled.

Figure 12. FPD-Link III Serial Stream

DS90UB947-Q1

www.ti.com

SNLS454A –NOVEMBER 2014 –REVISED MARCH 2019

Product Folder Links: DS90UB947-Q1

Feature Description (continued)

The device supports OpenLDI clocks in the range of 25 MHz to 96 MHz over one lane, or 50 MHz to 170 MHz

over two lanes. The FPD-Link III serial stream rate is 3.36 Gbps maximum (875 Mbps minimum) , or 2.975 Gbps

maximum per lane (875 Mbps minimum) when transmitting over both lanes.

7.3.2 Back Channel Data Transfer

The Backward Channel provides bidirectional communication between the display and host processor. The

information is carried from the deserializer to the serializer as serial frames. The back channel control data is

transferred over both serial links along with the high-speed forward data, DC balance coding and embedded

clock information. This architecture provides a backward path across the serial link together with a high-speed

forward channel. The back channel contains the I2C, CRC and 4 bits of standard GPIO information with 5, 10, or

20 Mbps line rate (configured by the compatible deserializer).

7.3.3 FPD-Link III Port Register Access

The DS90UB947-Q1 contains two downstream ports, therefore some registers must be duplicated to allow

control and monitoring of the two ports. To facilitate this, a TX_PORT_SEL register controls access to the two

sets of registers. Registers that are shared between ports (not duplicated) will be available independent of the

settings in the TX_PORT_SEL register.

Setting the TX_PORT0_SEL or TX_PORT1_SEL bit will allow a read of the register for the selected port. If both

bits are set, port1 registers will be returned. Writes will occur to ports for which the select bit is set, allowing

simultaneous writes to both ports if both select bits are set.

Setting the PORT1_I2C_EN bit will enable a second I

C slave address, allowing access to the second port

registers through the second I

C address. If this bit is set, the TX_PORT0_SEL and TX_PORT1_SEL bits will be

ignored.

7.3.4 OpenLDI Input Frame and Color Bit Mapping Select

The DS90UB947-Q1 can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes,

shown in Figure 13 and Figure 14. Each frame corresponds to a single pixel clock (PCLK) cycle. The LVDS clock

input to CLK± follows a 4:3 duty cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock

periods high, three low, and ending with two high. The mapping scheme is controlled by MAPSEL strap option or

by Register (Table 10).

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