Spartan-6 FPGA SelectIO Resources User Guide

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"Spartan-6+IO资源用户手册提供了关于如何使用Spartan-6 FPGA的输入/输出（IO）资源的详细指南，适用于设计与Xilinx硬件设备协同工作的方案。" Spartan-6 FPGA是Xilinx公司推出的一款FPGA（Field-Programmable Gate Array）芯片系列，它在嵌入式系统、通信、计算和各种工业应用中广泛应用。该系列FPGA具有丰富的逻辑单元、分布式存储器和I/O资源，使得它能够灵活地满足各种定制化需求。 SelectIO资源是Spartan-6 FPGA的一个关键特性，它涉及到芯片外部接口的配置和管理。SelectIO技术允许设计者根据应用需求调整I/O的性能参数，如速度、电压电平和驱动电流等。用户手册《Spartan-6 FPGA SelectIO Resources User Guide UG381(v1.3)》详细介绍了如何有效地利用这些资源进行系统设计。手册中可能涵盖的内容包括： 1. **I/O标准**：介绍支持的不同I/O标准，如LVCMOS、LVDS、HSTL、SSTL等，以及如何选择适合特定应用的I/O标准。 2. **I/O Bank**：解释Spartan-6 FPGA中的I/O Bank结构，每个Bank的特性，以及如何分配和配置I/O引脚。 3. **I/O缓冲**：描述输入和输出缓冲器的功能，包括速度等级、电压摆幅和驱动能力的配置。 4. **I/O串行化和解串化**：讨论如何使用串行/并行转换功能，以实现高速数据传输。 5. **时序分析**：提供有关满足时序约束的指导，确保正确操作I/O接口。 6. **电源管理**：介绍I/O电源的规划和管理，以降低功耗并提高系统稳定性。 7. **热插拔和ESD保护**：解释如何实现这些功能以增强系统的可靠性。 8. **设计示例和应用笔记**：提供实际案例，帮助用户理解和应用SelectIO特性。 9. **约束文件设置**：说明如何在硬件描述语言（如VHDL或Verilog）中定义和约束I/O资源。 10. **工具使用**：指导用户如何使用Xilinx的开发工具，如ISE（Integrated Software Environment）进行SelectIO资源的配置和仿真。请记住，Xilinx提供的文档仅供开发目的使用，并且在使用时应遵守其许可条款。由于文档内容不提供任何保修，用户在设计过程中需要自行承担风险。Xilinx保留随时更新文档而不事先通知的权利，且不对提供的技术支持或协助产生的任何问题承担责任。因此，设计者应密切关注Xilinx的最新更新和技术支持，以确保设计的准确性和兼容性。

Spartan-6 FPGA SelectIO Resources www.xilinx.com 15

UG381 (v1.3) March 15, 2010

Internal Termination

The DIFF_TERM attribute is set to TRUE to enable differential termination on a differential

I/O pin pair. This attribute uses the following syntax when used as a constraint in the UCF:

NET <I/O_NAME> DIFF_TERM = "<TRUE/FALSE>";

See Table 1-5, page 42 for bank compatibility of differential drivers, receivers, and optional

on-chip differential termination.

On-Chip Termination

Programmable input termination resistors and output driver impedance for single-ended

standards.

On-Chip Termination Benefits

Optional on-chip termination features in Spartan-6 FPGAs eliminate complex external

board termination schemes for high-speed single-ended signaling, such as those

commonly found in memory interfaces. Figure 1-6 shows an example of how on-chip

termination can remove the external termination resistors that can be found on a

unidirectional SSTL18 interface, such as a DDR2 SDRAM interface for address and control

pins. On-chip termination can optionally be used in the form of either programmable input

termination resistors and/or programmable output driver impedance (source

termination). Signal integrity simulations are always recommended for analyzing and

optimizing the I/O interfaces, and determining the best combination of programmable

I/O standards, optional internal termination features, and external termination

components. The best methodologies include using the Xilinx IBIS models, combined with

models for the other components on the board, and running IBIS signal integrity

simulations.

X-Ref Target - Figure 1-5

Figure 1-5: Input Termination Resistor Options for LVDS, RSDS, MINI_LVDS, and

PPDS I/O Standards

= 50Ω

100Ω

ug381_1_05_041709

a) Differential pairs with receivers using DIFF_TERM = FALSE constraint

b) Differential pairs with receivers using DIFF_TERM = TRUE constraint

DIFF_TERM = FALSE

DIFF_TERM = TRUE

Bank 0

Bank 2

Bank 0

Bank 2

Bank 4

Bank 3

Bank 5

Bank 1

Bank 0 and 2 Any Bank

16 www.xilinx.com Spartan-6 FPGA SelectIO Resources

UG381 (v1.3) March 15, 2010

Chapter 1: SelectIO Resources

Programmable Output Driver Impedance (Source Termination)

Programmable output driver impedance helps to eliminate reflections while avoiding the

need to use external source termination resistors in high-speed single-ended signaling

applications. The driver impedance is set through the use of the OUT_TERM attribute,

using NONE (default), UNTUNED_25, UNTUNED_50, or UNTUNED_75 to force the

output driver's impedance to be equal to the transmission line impedance of the printed

circuit board signal trace. Setting the OUT_TERM attribute to one of these values will

override the default value of NONE, and will also override all drive-strength and slew-

rates that the output buffer would have been set to for the assigned I/O standard. For

example, a bidirectional I/O assigned as LVCMOS25, 12 mA drive, slow slew rate, and

OUT_TERM = UNTUNED_50 would still have the input buffer set at LVCMOS25, but the

output buffer would no longer be configured for 12 mA drive and slow slew rate. Only

NONE (default), UNTUNED_50, or UNTUNED_75 are allowed for OUT_TERM when

CCO

is 1.2V or 1.5V in Bank 0 or Bank 2. In this case, UNTUNED_25 is not allowed.

The Spartan-6 FPGA programmable output driver impedance feature is similar to the DCI

feature available in many other Xilinx FPGA families. However, an important difference is

that the programmable output driver impedance is not calibrated, and therefore some

variation to the target output impedance value will exist across process, temperature, and

voltage variations. Proper evaluation of the system should always include signal integrity

analysis, ideally by using Xilinx IBIS models and running IBIS simulations.

X-Ref Target - Figure 1-6

Figure 1-6: Unidirectional SSTL18 Interface Using On-Chip Termination

SSTL18

ug381_1_06_110509

50Ω

100Ω

CCO

SSTL18

–

Typical External Resistors Used For a Unidirectional SSTL18 Interface

The Same Interface Using Optional Spartan-6 FPGA

On-Chip Termination Features At Both Ends

20Ω

= 50Ω

OUT_TERM = UNTUNED_50

IN_TERM = UNTUNED_SPLIT_50

Spartan-6 FPGA SelectIO Resources www.xilinx.com 17

UG381 (v1.3) March 15, 2010

Internal Termination

Figure 1-7 illustrates a controlled impedance driver in a Spartan-6 device.

To implement programmable output driver impedance on a given output pin, apply the

OUT_TERM attribute and set it to equal the desired target value. This attribute uses the

following syntax when specified as a constraint in the UCF:

NET <NET NAME> OUT_TERM = <NONE/ UNTUNED_25 / UNTUNED_50 / UNTUNED_75>;

Programmable Input Termination Resistors (Split Termination)

Some I/O standards (e.g., HSTL and SSTL) require input termination to help improve

signal integrity for high-speed single-ended signaling. (see Figure 1-8). Spartan-6 FPGA

I/Os contain optional on-chip input termination resistors that can reduce the need for

external resistors. The programmable input termination resistors are available for all of the

single-ended I/O standards. The structure is that of a pull-up and pull-down resistor in

parallel, providing a Thevenin-equivalent termination resistance to a V

CCO

/2 level. The

IN_TERM attribute can be set to NONE (default), UNTUNED_SPLIT_25,

UNTUNED_SPLIT_50, or UNTUNED_SPLIT_75. The input termination resistors will

always be present whenever the I/O is 3-stated, and instantly turned off when the output

buffer is enabled.

The Spartan-6 FPGA programmable input termination feature is similar to the DCI feature

available in many other Xilinx FPGA families. However, an important difference is that the

programmable input termination is not calibrated, and therefore some variation to the

target resistance values will exist. See the DC specification tables in the Spartan-6 FPGA

Data Sheet for more details. Proper evaluation of the system should always include signal

integrity analysis, ideally by using Xilinx IBIS models and running IBIS simulations.

X-Ref Target - Figure 1-7

Figure 1-7: Programmable Output Driver Impedance

ug381_c1_07_060509

OUT_TERM = UNTUNED_<25,50,75>

where 25, 50, or 75 is the value for R in Ω.

X-Ref Target - Figure 1-8

Figure 1-8: Input Termination for Split Termination

UG381_c1_08_060509

CCO

IN_TERM = UNTUNED_SPLIT_<25,50,75>

where 25, 50, or 75 is the value for R in Ω.

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