Xilinx Spartan-6 FPGA IO接口资源用户指南

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"XILINX SPARTAN6 IO说明书" Spartan-6 FPGA是Xilinx公司推出的一款中端FPGA（Field-Programmable Gate Array）系列，主要用于满足广泛的数字逻辑设计需求。该系列器件以其高效能、低功耗和成本效益而受到广泛应用。在Xilinx Spartan-6 FPGA中，I/O（Input/Output）资源是设计中的关键组成部分，它们决定了芯片如何与外部世界进行通信。 Spartan-6 FPGA的SelectIO技术是其I/O资源的核心特性之一，它提供了一种灵活的I/O配置，可以适应各种不同的接口标准和速度等级。SelectIO资源包括了输入接收器（Input Receiver）、输出驱动器（Output Driver）、输入输出缓冲器（Input/Output Buffer）以及可配置的均衡器、时钟处理和数据对齐功能。这些特性使得Spartan-6 FPGA能够支持从低速串行到高速并行的各种接口规范，如LVDS（Low-Voltage Differential Signaling）、PCIe（Peripheral Component Interconnect Express）、DDR（Double Data Rate）内存接口等。用户指南UG381详细介绍了Spartan-6 FPGA的SelectIO资源的使用方法，包括如何配置I/O标准、速度等级、电压摆幅、输入输出模式等。这本手册还涵盖了I/O Bank的概念，每个Bank包含了多个可配置的I/O资源，以实现布线优化和电源管理。此外，它还提供了关于I/O时序约束、I/O电源规划以及如何避免信号完整性问题的指导。在使用Spartan-6 FPGA进行设计时，必须遵循Xilinx提供的文档和许可条款。Xilinx明确表示，该文档仅供开发与Xilinx硬件设备兼容的设计使用，并且未经书面许可，不得复制、分发或以任何形式传播。同时，Xilinx不承担因使用文档产生的任何责任，并保留随时修改文档而不事先通知的权利。对于文档中的错误或遗漏，Xilinx没有义务进行修正，也不对因此产生的任何纠正或更新承担责任。 Xilinx Spartan-6 FPGA的I/O资源是实现高效、灵活系统设计的关键，而UG381用户指南则是理解和利用这些资源的重要参考。设计师需要仔细阅读和理解文档，以确保他们的设计符合规格要求，并且能够正确、稳定地运行。

Spartan-6 FPGA SelectIO Resources www.xilinx.com 15

UG381 (v1.3) March 15, 2010

Internal Termination

The DIFF_TERM attribute is set to TRUE to enable differential termination on a differential

I/O pin pair. This attribute uses the following syntax when used as a constraint in the UCF:

NET <I/O_NAME> DIFF_TERM = "<TRUE/FALSE>";

See Table 1-5, page 42 for bank compatibility of differential drivers, receivers, and optional

on-chip differential termination.

On-Chip Termination

Programmable input termination resistors and output driver impedance for single-ended

standards.

On-Chip Termination Benefits

Optional on-chip termination features in Spartan-6 FPGAs eliminate complex external

board termination schemes for high-speed single-ended signaling, such as those

commonly found in memory interfaces. Figure 1-6 shows an example of how on-chip

termination can remove the external termination resistors that can be found on a

unidirectional SSTL18 interface, such as a DDR2 SDRAM interface for address and control

pins. On-chip termination can optionally be used in the form of either programmable input

termination resistors and/or programmable output driver impedance (source

termination). Signal integrity simulations are always recommended for analyzing and

optimizing the I/O interfaces, and determining the best combination of programmable

I/O standards, optional internal termination features, and external termination

components. The best methodologies include using the Xilinx IBIS models, combined with

models for the other components on the board, and running IBIS signal integrity

simulations.

X-Ref Target - Figure 1-5

Figure 1-5: Input Termination Resistor Options for LVDS, RSDS, MINI_LVDS, and

PPDS I/O Standards

= 50Ω

100Ω

ug381_1_05_041709

a) Differential pairs with receivers using DIFF_TERM = FALSE constraint

b) Differential pairs with receivers using DIFF_TERM = TRUE constraint

DIFF_TERM = FALSE

DIFF_TERM = TRUE

Bank 0

Bank 2

Bank 0

Bank 2

Bank 4

Bank 3

Bank 5

Bank 1

Bank 0 and 2 Any Bank

16 www.xilinx.com Spartan-6 FPGA SelectIO Resources

UG381 (v1.3) March 15, 2010

Chapter 1: SelectIO Resources

Programmable Output Driver Impedance (Source Termination)

Programmable output driver impedance helps to eliminate reflections while avoiding the

need to use external source termination resistors in high-speed single-ended signaling

applications. The driver impedance is set through the use of the OUT_TERM attribute,

using NONE (default), UNTUNED_25, UNTUNED_50, or UNTUNED_75 to force the

output driver's impedance to be equal to the transmission line impedance of the printed

circuit board signal trace. Setting the OUT_TERM attribute to one of these values will

override the default value of NONE, and will also override all drive-strength and slew-

rates that the output buffer would have been set to for the assigned I/O standard. For

example, a bidirectional I/O assigned as LVCMOS25, 12 mA drive, slow slew rate, and

OUT_TERM = UNTUNED_50 would still have the input buffer set at LVCMOS25, but the

output buffer would no longer be configured for 12 mA drive and slow slew rate. Only

NONE (default), UNTUNED_50, or UNTUNED_75 are allowed for OUT_TERM when

CCO

is 1.2V or 1.5V in Bank 0 or Bank 2. In this case, UNTUNED_25 is not allowed.

The Spartan-6 FPGA programmable output driver impedance feature is similar to the DCI

feature available in many other Xilinx FPGA families. However, an important difference is

that the programmable output driver impedance is not calibrated, and therefore some

variation to the target output impedance value will exist across process, temperature, and

voltage variations. Proper evaluation of the system should always include signal integrity

analysis, ideally by using Xilinx IBIS models and running IBIS simulations.

X-Ref Target - Figure 1-6

Figure 1-6: Unidirectional SSTL18 Interface Using On-Chip Termination

SSTL18

ug381_1_06_110509

50Ω

100Ω

CCO

SSTL18

–

Typical External Resistors Used For a Unidirectional SSTL18 Interface

The Same Interface Using Optional Spartan-6 FPGA

On-Chip Termination Features At Both Ends

20Ω

= 50Ω

OUT_TERM = UNTUNED_50

IN_TERM = UNTUNED_SPLIT_50

Spartan-6 FPGA SelectIO Resources www.xilinx.com 17

UG381 (v1.3) March 15, 2010

Internal Termination

Figure 1-7 illustrates a controlled impedance driver in a Spartan-6 device.

To implement programmable output driver impedance on a given output pin, apply the

OUT_TERM attribute and set it to equal the desired target value. This attribute uses the

following syntax when specified as a constraint in the UCF:

NET <NET NAME> OUT_TERM = <NONE/ UNTUNED_25 / UNTUNED_50 / UNTUNED_75>;

Programmable Input Termination Resistors (Split Termination)

Some I/O standards (e.g., HSTL and SSTL) require input termination to help improve

signal integrity for high-speed single-ended signaling. (see Figure 1-8). Spartan-6 FPGA

I/Os contain optional on-chip input termination resistors that can reduce the need for

external resistors. The programmable input termination resistors are available for all of the

single-ended I/O standards. The structure is that of a pull-up and pull-down resistor in

parallel, providing a Thevenin-equivalent termination resistance to a V

CCO

/2 level. The

IN_TERM attribute can be set to NONE (default), UNTUNED_SPLIT_25,

UNTUNED_SPLIT_50, or UNTUNED_SPLIT_75. The input termination resistors will

always be present whenever the I/O is 3-stated, and instantly turned off when the output

buffer is enabled.

The Spartan-6 FPGA programmable input termination feature is similar to the DCI feature

available in many other Xilinx FPGA families. However, an important difference is that the

programmable input termination is not calibrated, and therefore some variation to the

target resistance values will exist. See the DC specification tables in the Spartan-6 FPGA

Data Sheet for more details. Proper evaluation of the system should always include signal

integrity analysis, ideally by using Xilinx IBIS models and running IBIS simulations.

X-Ref Target - Figure 1-7

Figure 1-7: Programmable Output Driver Impedance

ug381_c1_07_060509

OUT_TERM = UNTUNED_<25,50,75>

where 25, 50, or 75 is the value for R in Ω.

X-Ref Target - Figure 1-8

Figure 1-8: Input Termination for Split Termination

UG381_c1_08_060509

CCO

IN_TERM = UNTUNED_SPLIT_<25,50,75>

where 25, 50, or 75 is the value for R in Ω.

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