JEDEC发布JESD209-5B：LPDDR5内存新标准，含可选LPDDR5X扩展
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收藏 8.98MB PDF 举报 "JEDEC JESD209-5B是2021年发布的最新版低功耗双倍数据速率5 (LPDDR5) 标准，它旨在优化性能、降低功耗并增强内存系统的灵活性。此版本中包含了对LPDDR5X的扩展规范，进一步提升了内存的速度和可靠性。"
JEDEC JESD209-5B标准是固态技术协会对低功耗内存技术的最新贡献，主要针对LPDDR5 DRAM进行了一系列升级。这一标准由JEDEC的JC-42.6低功耗存储器小组委员会负责制定。新标准的核心亮点在于以下几个方面：
1. **速率提升**：LPDDR5X在JESD209-5B中的速率被扩展到了8533 Mbps，相比之前版本的6400 Mbps有了显著提升，这意味着更快的数据传输速度，对于处理大数据量和高频率计算的应用来说至关重要。
2. **信号完整性改善**：通过引入TX/RX收发均衡技术，标准提高了信号质量，降低了由于高速传输导致的信号损失和干扰，确保数据在内存系统中的准确无误传输。
3. **自适应刷新管理**：新标准添加了自适应刷新管理功能，增强了内存的可靠性。这有助于在各种工作条件下保持数据完整性，特别是在应对电源波动和环境变化时，能有效保护内存中的信息不丢失。
4. **LPDDR5X扩展**：LPDDR5X是一个可选的扩展，专为满足5G通信等高性能应用需求设计。它提供了更高的带宽，简化了架构，使得设备能够更高效地处理高速网络下的数据流量，从而提升整体系统性能。
JEDEC标准的制定遵循严格的程序，旨在促进制造商和消费者之间的理解和互换性，推动产品的持续改进，并帮助消费者迅速找到适用的产品。尽管标准的制定不受任何专利影响，但采用这些标准的各方仍需注意可能存在的知识产权问题。
JESD209-5B标准对LPDDR5内存的升级，不仅提升了移动设备和数据中心的内存性能，还为未来的5G通信和高性能计算应用奠定了坚实的基础。随着技术的发展，内存的标准也将不断演进，以适应不断提升的计算需求。
JEDEC Standard No. 209-5B
xiv
Figure 234 — Temp Sensor Timing ............................................................................................... 404
Figure 235 — Interval oscillator offset_temp ................................................................................. 408
Figure 236 — Interval oscillator offset_volt ................................................................................... 408
Figure 237 — In case of WCK2DQI Interval Oscillator is stopped by MPC Command ...................... 411
Figure 238 — In case of WCK2DQI Interval Oscillator is stopped by Interval Timer ........................ 411
Figure 239 — In case of WCK2DQO Interval Oscillator is stopped by MPC Command .................... 412
Figure 240 — In case of WCK2DQO Interval Oscillator is stopped by Interval Timer ....................... 412
Figure 241 — WCK2DQI/WCK2DQO Interval Oscillator Start/Stop Command Constraints Timing .. 413
Figure 242 — DVFSC High (VDD2H) to Low (VDD2L) Transition ................................................ 415
Figure 243 — DVFSC Low (VDD2L) to High (VDD2H) Transition ................................................ 415
Figure 244 — Example DVFSC Block Diagram ............................................................................. 416
Figure 245 —DVFSQ High (VDDQ) to Low Transition Flow Chart ................................................ 417
Figure 246 — DVFSQ High (VDDQ) to Low Transition Timing ..................................................... 417
Figure 247 — DVFSQ Low (VDDQ) to High (VDDQ) Transition Flow Chart without VRCG ........... 418
Figure 248 — DVFSQ Low (VDDQ) to High Transition Timing without VRCG during VddQ ramp .. 419
Figure 249 — DVFSQ Low (VDDQ) to High (VDDQ) Transition Flow Chart with VRCG ............... 420
Figure 250 — DVFSQ Low (VDDQ) to High Transition with VRCG .............................................. 420
Figure 251 — Data copy granularity and reference data configuration in BL32 ................................. 421
Figure 252 — Example of Write Data Copy Function Timing Diagram ............................................ 423
Figure 253 — Example of Read Data Copy Function Timing Diagram ............................................. 425
Figure 254 — Write X timing at Sync off: BG Mode, CKR (WCK vs. CK) = 4:1, BL=16 .................. 427
Figure 255 — Consecutive Write and Write X timing at Sync off: BG Mode, CKR (WCK vs.
CK) = 4:1, BL=16 ................................................................................................ 427
Figure 256 — Consecutive Write and Write X timing at Sync: BG Mode, CKR (WCK vs.
CK) = 4:1, BL=16 ................................................................................................ 428
Figure 257 — Write w/ write X issuing timing at Sync state. ........................................................... 428
Figure 258 — CAS_WRX Command timing after WCK2CK sync state is expired ............................ 429
Figure 259 — Guard Key Timing Diagram .................................................................................... 431
Figure 260 — PPR Timing ........................................................................................................... 432
Figure 261 — DFE pre-drive requirement ...................................................................................... 440
Figure 262 — Per-pin DFE pre-drive requirement .......................................................................... 441
Figure 263 — Example of DFE quantities of DQ bits...................................................................... 442
Figure 264 — Write command showing link ECC transfer .............................................................. 443
Figure 265 — Read command showing Link ECC transfer .............................................................. 444
Figure 266 — Data flow on a memory Write operation ................................................................... 447
Figure 267 — Data flow on a memory Read operation .................................................................... 448
Figure 268 — Timing Relationship among CK, WCK and RDQS .................................................... 451
Figure 269 — SE to Differential CK and Write DQS -FSP Switching Timing ................................... 452
Figure 270 — Differential to SE CK and Write DQS -FSP Switching Timing ................................... 453
Figure 271 — VRCG status change to high current mode: Single-ended Clock Case ......................... 454
Figure 272 — VRCG status change to high current mode: Differential Clock Case ........................... 454
Figure 273 — Enhanced WCK Always On Mode Timing Example .................................................. 457
Figure 274 — Write Timing Diagram (BG mode, CKR=4:1, BL32) Example for BL/n, BL/n_min
and BL/n_max ...................................................................................................... 460
Figure 275 — DC Voltage Range .................................................................................................. 504
Figure 276 — VDDQ Tolerance Definition in Allowable Range ...................................................... 504
Figure 277 — Zprofile Z(f) of the system at the DRAM package solder ball (without the DRAM
component) .......................................................................................................... 505
Figure 278 — A simplified Z(f) system electrical model and frequency response of the behavioral PDN
electrical load model without the DRAM component per voltage domain per channel. 506
Figure 279 — Overshoot and Undershoot Definition ...................................................................... 510
Figure 280 — CK Differential Input Voltage .................................................................................. 510
Figure 281 — Definition of differential Clock Peak Voltage ............................................................ 511
Figure 282 — Clock Single ended Input Voltage ............................................................................ 512
Figure 283 — Differential Input Slew Rate Definition for CK_t, CK_c ............................................ 513
Figure 284 — Differential Input Slew Rate Definition for CK_t, CK_c ............................................ 514
Figure 285 — WCK Differential Input Voltage ............................................................................... 515
Figure 286 — Definition of differential WCK Peak Voltage ............................................................ 516
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