JEDEC发布JESD209-5B：LPDDR5内存新标准，含可选LPDDR5X扩展

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"JEDEC JESD209-5B是2021年发布的最新版低功耗双倍数据速率5 (LPDDR5) 标准，它旨在优化性能、降低功耗并增强内存系统的灵活性。此版本中包含了对LPDDR5X的扩展规范，进一步提升了内存的速度和可靠性。" JEDEC JESD209-5B标准是固态技术协会对低功耗内存技术的最新贡献，主要针对LPDDR5 DRAM进行了一系列升级。这一标准由JEDEC的JC-42.6低功耗存储器小组委员会负责制定。新标准的核心亮点在于以下几个方面： 1. **速率提升**：LPDDR5X在JESD209-5B中的速率被扩展到了8533 Mbps，相比之前版本的6400 Mbps有了显著提升，这意味着更快的数据传输速度，对于处理大数据量和高频率计算的应用来说至关重要。 2. **信号完整性改善**：通过引入TX/RX收发均衡技术，标准提高了信号质量，降低了由于高速传输导致的信号损失和干扰，确保数据在内存系统中的准确无误传输。 3. **自适应刷新管理**：新标准添加了自适应刷新管理功能，增强了内存的可靠性。这有助于在各种工作条件下保持数据完整性，特别是在应对电源波动和环境变化时，能有效保护内存中的信息不丢失。 4. **LPDDR5X扩展**：LPDDR5X是一个可选的扩展，专为满足5G通信等高性能应用需求设计。它提供了更高的带宽，简化了架构，使得设备能够更高效地处理高速网络下的数据流量，从而提升整体系统性能。 JEDEC标准的制定遵循严格的程序，旨在促进制造商和消费者之间的理解和互换性，推动产品的持续改进，并帮助消费者迅速找到适用的产品。尽管标准的制定不受任何专利影响，但采用这些标准的各方仍需注意可能存在的知识产权问题。 JESD209-5B标准对LPDDR5内存的升级，不仅提升了移动设备和数据中心的内存性能，还为未来的5G通信和高性能计算应用奠定了坚实的基础。随着技术的发展，内存的标准也将不断演进，以适应不断提升的计算需求。

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JEDEC Standard No. 209-5B

xiv

Figure 234 — Temp Sensor Timing ............................................................................................... 404

Figure 235 — Interval oscillator offset_temp ................................................................................. 408

Figure 236 — Interval oscillator offset_volt ................................................................................... 408

Figure 237 — In case of WCK2DQI Interval Oscillator is stopped by MPC Command ...................... 411

Figure 238 — In case of WCK2DQI Interval Oscillator is stopped by Interval Timer ........................ 411

Figure 239 — In case of WCK2DQO Interval Oscillator is stopped by MPC Command .................... 412

Figure 240 — In case of WCK2DQO Interval Oscillator is stopped by Interval Timer ....................... 412

Figure 241 — WCK2DQI/WCK2DQO Interval Oscillator Start/Stop Command Constraints Timing .. 413

Figure 242 — DVFSC High (VDD2H) to Low (VDD2L) Transition ................................................ 415

Figure 243 — DVFSC Low (VDD2L) to High (VDD2H) Transition ................................................ 415

Figure 244 — Example DVFSC Block Diagram ............................................................................. 416

Figure 245 —DVFSQ High (VDDQ) to Low Transition Flow Chart ................................................ 417

Figure 246 — DVFSQ High (VDDQ) to Low Transition Timing ..................................................... 417

Figure 247 — DVFSQ Low (VDDQ) to High (VDDQ) Transition Flow Chart without VRCG ........... 418

Figure 248 — DVFSQ Low (VDDQ) to High Transition Timing without VRCG during VddQ ramp .. 419

Figure 249 — DVFSQ Low (VDDQ) to High (VDDQ) Transition Flow Chart with VRCG ............... 420

Figure 250 — DVFSQ Low (VDDQ) to High Transition with VRCG .............................................. 420

Figure 251 — Data copy granularity and reference data configuration in BL32 ................................. 421

Figure 252 — Example of Write Data Copy Function Timing Diagram ............................................ 423

Figure 253 — Example of Read Data Copy Function Timing Diagram ............................................. 425

Figure 254 — Write X timing at Sync off: BG Mode, CKR (WCK vs. CK) = 4:1, BL=16 .................. 427

Figure 255 — Consecutive Write and Write X timing at Sync off: BG Mode, CKR (WCK vs.

CK) = 4:1, BL=16 ................................................................................................ 427

Figure 256 — Consecutive Write and Write X timing at Sync: BG Mode, CKR (WCK vs.

CK) = 4:1, BL=16 ................................................................................................ 428

Figure 257 — Write w/ write X issuing timing at Sync state. ........................................................... 428

Figure 258 — CAS_WRX Command timing after WCK2CK sync state is expired ............................ 429

Figure 259 — Guard Key Timing Diagram .................................................................................... 431

Figure 260 — PPR Timing ........................................................................................................... 432

Figure 261 — DFE pre-drive requirement ...................................................................................... 440

Figure 262 — Per-pin DFE pre-drive requirement .......................................................................... 441

Figure 263 — Example of DFE quantities of DQ bits...................................................................... 442

Figure 264 — Write command showing link ECC transfer .............................................................. 443

Figure 265 — Read command showing Link ECC transfer .............................................................. 444

Figure 266 — Data flow on a memory Write operation ................................................................... 447

Figure 267 — Data flow on a memory Read operation .................................................................... 448

Figure 268 — Timing Relationship among CK, WCK and RDQS .................................................... 451

Figure 269 — SE to Differential CK and Write DQS -FSP Switching Timing ................................... 452

Figure 270 — Differential to SE CK and Write DQS -FSP Switching Timing ................................... 453

Figure 271 — VRCG status change to high current mode: Single-ended Clock Case ......................... 454

Figure 272 — VRCG status change to high current mode: Differential Clock Case ........................... 454

Figure 273 — Enhanced WCK Always On Mode Timing Example .................................................. 457

Figure 274 — Write Timing Diagram (BG mode, CKR=4:1, BL32) Example for BL/n, BL/n_min

and BL/n_max ...................................................................................................... 460

Figure 275 — DC Voltage Range .................................................................................................. 504

Figure 276 — VDDQ Tolerance Definition in Allowable Range ...................................................... 504

Figure 277 — Zprofile Z(f) of the system at the DRAM package solder ball (without the DRAM

component) .......................................................................................................... 505

Figure 278 — A simplified Z(f) system electrical model and frequency response of the behavioral PDN

electrical load model without the DRAM component per voltage domain per channel. 506

Figure 279 — Overshoot and Undershoot Definition ...................................................................... 510

Figure 280 — CK Differential Input Voltage .................................................................................. 510

Figure 281 — Definition of differential Clock Peak Voltage ............................................................ 511

Figure 282 — Clock Single ended Input Voltage ............................................................................ 512

Figure 283 — Differential Input Slew Rate Definition for CK_t, CK_c ............................................ 513

Figure 284 — Differential Input Slew Rate Definition for CK_t, CK_c ............................................ 514

Figure 285 — WCK Differential Input Voltage ............................................................................... 515

Figure 286 — Definition of differential WCK Peak Voltage ............................................................ 516

JEDEC Standard No. 209-5B

Figure 287 — WCK Single ended Input Voltage ............................................................................. 517

Figure 288 — Differential Input Slew Rate Definition for WCK_t, WCK_c ..................................... 518

Figure 289 — Vix Definition (WCK)............................................................................................. 519

Figure 290 — Single Ended Output Slew Rate Definition ............................................................... 520

Figure 291 — Differential Output Slew Rate Definition .................................................................. 521

Figure 292 — Driver Output Reference Load for Timing ................................................................ 522

Figure 293 — Single Ended Mode WCK input Voltage ................................................................... 523

Figure 294 — Single Ended Mode WCK pulse ............................................................................... 523

Figure 295 — Single Ended Mode CK input Voltage ...................................................................... 524

Figure 296 — Single Ended Mode CK pulse .................................................................................. 525

Figure 297 — tLZ(RDQS) method for calculating transitions and end point ..................................... 526

Figure 298 — tHZ(RDQS) method for calculating transitions and end point ..................................... 527

Figure 299 — tLZ(DQ) method for calculating transitions and end point .......................................... 528

Figure 300 — tHZ(DQ) method for calculating transitions and end point ......................................... 529

Figure 301 — N-UI DQ to RDQS output timing definitions ............................................................ 555

Figure 302 — tQW example of eyewidth per pin and relationship of tDQSQ(pin) and tQH(pin)

across byte group .................................................................................................. 556

Figure 303 — Read burst example for pin DQx depicting bits 0 and 5 relative to the RDQS edge

for 0 UI mismatch ................................................................................................. 557

Figure 304 — Read burst example for pin DQx depicting bits 0 and 5 relative to the RDQS edge

for 3 UI mismatch ................................................................................................. 557

Figure 305 — Synchronous mode CS Rx Mask definition ............................................................... 559

Figure 306 — Synchronous mode CS Rx single pulse definition ...................................................... 559

Figure 307 — Synchronous mode CS Timings at the DRAM Pin ..................................................... 560

Figure 308 — Asynchronous mode ViHPD and ViLPD at Power Down Exit .................................... 560

Figure 309 — CA Rx Mask definition ........................................................................................... 562

Figure 310 — CA Rx single pulse definition .................................................................................. 562

Figure 311 — CA timings at the DRAM Pins ................................................................................. 563

Figure 312 — CK_t Rising Edge CA mask .................................................................................... 565

Figure 313 — CK_t Falling Edge CA mask .................................................................................... 565

Figure 314 — DQ, DMI, Parity and DBI Rx Mask definition .......................................................... 566

Figure 315 — DQ to WCK tWCK2DQI and tDQ2DQ Timings at the DRAM pins referenced

from the internal latch ........................................................................................... 566

Figure 316 — DQ, DMI, Parity and DBI Rx single pulse definition ................................................. 567

Figure 317 — LPDDR5X DQ single input pulse definition ............................................................. 569

Figure 318 — Example of rank assignment for a single-channel dual-rank package ........................... 573

Figure 319 — Example of rank assignment for a single-channel dual-rank package ........................... 581

JEDEC Standard No. 209-5B

xvi

Tables

Table 1 — Pad Definition and Description ......................................................................................... 3

Table 2 — Pins Per-Byte Signal List/Description for Link Protection disabled ...................................... 4

Table 3 — Pins Per-Byte Signal List/Description for Link Protection enabled ....................................... 4

Table 4 — LPDDR5 Address Translation Table .................................................................................. 8

Table 5 — LPDDR5X Address Translation Table .............................................................................. 8

Table 6 — LPDDR5 SDRAM x16 mode Addressing for BG Mode (4Banks/4Bank Groups) ................ 14

Table 7 — LPDDR5 SDRAM x8 mode Addressing for BG Mode ...................................................... 15

Table 8 — LPDDR5 SDRAM x16 mode Addressing for 8B Mode (Does not apply to LPDDR5X

SDRAM) ............................................................................................................... 16

Table 9 — LPDDR5 SDRAM x8 mode Addressing for 8B Mode (Does not apply to LPDDR5X

SDRAM) ............................................................................................................... 17

Table 10 — LPDDR5 SDRAM x16 mode Addressing for 16B Mode ................................................. 18

Table 11 — LPDDR5 SDRAM x8 mode Addressing for 16B Mode ................................................... 19

Table 12 — LPDDR5 Speed Grades ................................................................................................ 20

Table 13 — LPDDR5X Speed Grades ............................................................................................. 21

Table 14 — Burst Sequence for READ (8bank mode) (Not applicable to LPDDR5X SDRAM) ............ 22

Table 15 — Burst Sequence for READ (4bank/ 4Bank Group mode or 16Bank mode) ........................ 22

Table 16 — Burst sequence for Write .............................................................................................. 22

Table 17 — Example Clock and Interface Signal Frequency Relationship ........................................... 25

Table 18 — MRS Default setting..................................................................................................... 26

Table 19 — Voltage Ramp Conditions ............................................................................................. 26

Table 20 — Initialization Timing Parameters .................................................................................... 29

Table 21 — Reset Timing Parameter ............................................................................................... 31

Table 22 — Power Supply Conditions ............................................................................................. 31

Table 23 — Power Supply Conditions ............................................................................................. 31

Table 24 — ZQ Calibration Timing Parameters ................................................................................ 39

Table 25 — Relation between MR16 OP[3:2] Setting and Physical Register Number .......................... 47

Table 26 — Relation between MR16 OP[1:0] Setting and Physical Register Number .......................... 47

Table 27 — Mapping of CA Input pin and DQ Output pin ................................................................. 49

Table 28 — Command Bus Training AC Timing Table ...................................................................... 55

Table 29 — Mapping of MR12 OP Code and DQ Numbers ............................................................... 63

Table 30 — Mapping of CA Input pin and DQ Output pin ................................................................. 63

Table 31 — Command Bus Training AC Timing Table ...................................................................... 70

Table 32 — WCK2CK Leveling Timing Parameters ......................................................................... 79

Table 33 — Duty Cycle Adjuster Range .......................................................................................... 81

Table 34 — Read DCA Range ........................................................................................................ 84

Table 35 — DCM output example ................................................................................................... 87

Table 36 — Duty cycle monitor timing ............................................................................................ 87

Table 37 — Invert Mask or output data fix0 Assignments in X16 Mode ............................................. 89

Table 38 — Invert Mask or output data fix0 Assignments in X8 Mode ............................................... 89

Table 39 — Read DQ Calibration Bit Ordering, Inversion, output data fix0 example for DQ ............... 92

Table 40 — Read DQ Calibration Bit Ordering, Inversion, output data fix0 example for DMI .............. 92

Table 41 — DMI Output behavior and Read Latencies for Read DQ Cal. command ............................ 94

Table 42 — Relationship between MR setting and DMI behavior for RDC command.......................... 94

Table 43 — Relationship between MR setting and FIFO behavior ...................................................... 97

Table 44 — DMI, RDQS_t/Parity Input behavior for Write FIFO command ....................................... 98

Table 45 — DMI Output behavior and Read Latencies for Read FIFO command ................................ 99

Table 46 — Relationship between MR setting and DMI behavior for RFF and RDC command ............ 99

Table 47 — MR# and Operand which are prohibited to change during RDQS toggle mode. ............... 108

Table 48 — MR# and Operand which are prohibited to change during Enhanced RDQS

training mode ...................................................................................................... 111

Table 49 — Enhanced RQDS training mode entry and exit timings .................................................. 113

Table 50 — Relationship among RDQS_t, Input data and data written to cell.................................... 114

Table 51 — Read/Write-based RDQS_t training mode entry and exit timings ................................... 115

Table 52 — Relationship between MR setting and Read/Write-based WCK-RDQS_t Training ........... 115

Table 53 — DMI, RDQS_t/Parity Input behavior for Read/Write-based WCK-RDQS_t Training ....... 116

Table 54 — DMI behavior and Read Latencies for Read/Write-based WCK-RDQS_t Training .......... 116

JEDEC Standard No. 209-5B

xvii

Table 55 — Rx Offset Calibration Training Time Parameter ........................................................... 117

Table 56 — Mode Register Assignment in LPDDR5 SDRAM (MR8 OP[1:0]=00

) .......................... 123

Table 57 — Mode Register Assignment in LPDDR5X SDRAM (MR8 OP[1:0]=01

) ....................... 126

Table 58 — MR0 Register Information (MA [6:0] = 00

) ............................................................... 130

Table 59 — MR0 definition .......................................................................................................... 130

Table 60 — MR1 Register Information (MA[5:0] = 01

) ................................................................ 131

Table 61 — MR1 definition .......................................................................................................... 131

Table 62 — MR2 Register Information (MA [6:0] = 02

) ............................................................... 133

Table 63 — MR2 Register definition ............................................................................................. 133

Table 64 — nWR Latency ............................................................................................................ 136

Table 65 — MR3 Register Information (MA[7:0] = 03

) ................................................................ 137

Table 66 — MR3 Definition ......................................................................................................... 137

Table 67 — MR4 Register Information (MA[7:0] = 04

) ................................................................ 138

Table 68 — MR4 definition .......................................................................................................... 138

Table 69 — MR5 Register Information (MA[7:0] = 05

) ................................................................ 139

Table 70 — MR5 Definition ......................................................................................................... 139

Table 71 — MR6 Register Information (MA[7:0] = 06

) ................................................................ 139

Table 72 — MR6 Definition ......................................................................................................... 139

Table 73 — MR7 Register Information (MA[7:0] = 07

) ................................................................ 139

Table 74 — MR7 Definition ......................................................................................................... 139

Table 75 — MR8 Register Information (MA[7:0] = 08

) ................................................................ 140

Table 76 — MR8 Definition ......................................................................................................... 140

Table 77 — MR9 Register Information (MA[7:0] = 09

) ................................................................ 140

Table 78 — MR9 Definition ......................................................................................................... 140

Table 79 — MR10 Register Information (MA [7:0] = 0A

) ............................................................. 141

Table 80 — MR10 Definition ....................................................................................................... 141

Table 81 — MR11 Register Information (MA[7:0] = 0B

) .............................................................. 142

Table 82 — MR11 Definition ........................................................................................................ 142

Table 83 — MR12 Register Information (MA[5:0] = 0C

) .............................................................. 143

Table 84 — MR12 Definition ....................................................................................................... 143

Table 85 — MR12 V

REF

(CA) Settings ........................................................................................... 144

Table 86 — MR13 Register Information (MA[5:0] = 0D

) .............................................................. 145

Table 87 — MR13 Definition ....................................................................................................... 145

Table 88 — MR14 Register Information (MA[7:0] = 0E

) .............................................................. 146

Table 89 — MR14 definition ........................................................................................................ 146

Table 90 — MR14 V

REF

(DQ[7:0]) Settings .................................................................................... 147

Table 91 — MR15 Register Information (MA[6:0] = 0F

) .............................................................. 149

Table 92 — MR15 definition ........................................................................................................ 149

Table 93 — OP[6:0] VREF(DQ[15:8]) Settings .............................................................................. 150

Table 94 — MR16 Register Information (MA[5:0] = 10

) ............................................................... 152

Table 95 — MR16 definition ........................................................................................................ 152

Table 96 — MR17 Register Information (MA[5:0] = 11

) ............................................................... 153

Table 97 — MR17 definition ........................................................................................................ 153

Table 98 — MR18 Register Information (MA[7:0] = 12

) .............................................................. 154

Table 99 — MR18 Definition ....................................................................................................... 154

Table 100 — MR19 Register Information (MA[5:0] = 13

) ............................................................. 155

Table 101 — MR19 Definition ...................................................................................................... 155

Table 102 — MR20 Register Information (MA[7:0] = 14

) ............................................................. 156

Table 103 — MR20 definition ...................................................................................................... 156

Table 104 — MR21 Register Information (MA[7:0] = 15

) ............................................................. 157

Table 105 — MR21 Definition ...................................................................................................... 157

Table 106 — MR22 Register Information (MA[7:0] = 16

) ............................................................. 158

Table 107 — MR22 Definition ...................................................................................................... 158

Table 108 — MR23 Register Information (MA[5:0] = 17H) ............................................................ 158

Table 109 — MR23 Definition ...................................................................................................... 158

Table 110 — Row Address of Masked Segment for x16 Mode ......................................................... 158

Table 111 — Row Address of Masked Segment for x8 Mode ........................................................... 158

Table 112 — MR24 Register Information (MA[5:0]=18

) .............................................................. 159

JEDEC Standard No. 209-5B

xviii

Table 113 — MR24 Definition ..................................................................................................... 159

Table 114 — MR25 Register Information (MA[7:0] = 19

) ............................................................. 160

Table 115 — MR25 Definition ..................................................................................................... 160

Table 116 — MR26 Register Information (MA[7:0] = 1A

) ............................................................ 161

Table 117 — MR26 definition ...................................................................................................... 161

Table 118 — MR27 Register Information (MA[7:0] = 1B

) ............................................................ 162

Table 119 — MR27 Definition ...................................................................................................... 162

Table 120 — MR28 Register Information (MA[7:0] = 1C

) ............................................................ 163

Table 121 — MR28 Definition ...................................................................................................... 163

Table 122 — MR29 Register Information (MA[7:0] = 1

) ............................................................. 164

Table 123 — MR29 Definition ..................................................................................................... 164

Table 124 — MR30 Register Information (MA[5:0] = 1E

) ............................................................ 165

Table 125 — MR30 Definition ...................................................................................................... 165

Table 126 — MR31 Register Information (MA[7:0] = 1F

) ............................................................. 166

Table 127 — MR31 Definition ...................................................................................................... 166

Table 128 — MR31 Invert Register Pin Mapping ........................................................................... 166

Table 129 — MR32 Register Information (MA[7:0] = 20

) ............................................................. 167

Table 130 — MR32 definition ...................................................................................................... 167

Table 131 — MR32 Invert Register Pin Mapping ........................................................................... 167

Table 132 — MR33 Register Information (MA[7:0] = 21

) ............................................................. 168

Table 133 — MR33 Definition ...................................................................................................... 168

Table 134 — MR34 Register Information (MA[7:0] = 22

) ............................................................. 168

Table 135 — MR34 Definition ...................................................................................................... 168

Table 136 — MR35 Register Information (MA[7:0] = 23

) ............................................................. 169

Table 137 — MR35 Definition ...................................................................................................... 169

Table 138 — MR36 Register Information (MA[7:0] = 24

) ............................................................. 169

Table 139 — MR36 Definition ...................................................................................................... 169

Table 140 — MR37 Register Information (MA[7:0] = 25

) ............................................................. 170

Table 141 — MR37 Definition ...................................................................................................... 170

Table 142 — MR38 Register Information (MA[7:0] = 26

) ............................................................. 171

Table 143 — MR38 Definition ...................................................................................................... 171

Table 144 — MR39 Register Information (MA[7:0] = 27

) ............................................................. 171

Table 145 — MR39 Definition ...................................................................................................... 171

Table 146 — MR40 Register Information (MA[7:0] = 28

) ............................................................. 172

Table 147 — MR40 Definition ...................................................................................................... 172

Table 148 — MR41 Register Information (MA[6:0] = 29

) ............................................................. 173

Table 149 — MR41 definition ...................................................................................................... 173

Table 150 — MR42 Register Information (MA[7:0] = 2A

) ............................................................ 173

Table 151 — MR42 definition ...................................................................................................... 173

Table 152 — MR43 Register Information (MA[7:0] = 2B

) ............................................................ 174

Table 153 — MR43 definition ...................................................................................................... 174

Table 154 — MR44 Register Information (MA[7:0] = 2C

) ............................................................ 175

Table 155 — MR44 definition ...................................................................................................... 175

Table 156 — MR45 Register Information (MA[7:0] = 2D

) ............................................................ 176

Table 157 — MR45 definition ...................................................................................................... 176

Table 158 — Updating ECC Syndromes and Error Byte Lane ......................................................... 177

Table 159 — MR46 Register Information (MA[5:0] = 2E

) ............................................................ 177

Table 160 — MR46 definition ...................................................................................................... 177

Table 161 — MR47 Register Information (MA[7:0] = 2F

) ............................................................. 177

Table 162 — MR47 Definition ...................................................................................................... 177

Table 163 — MR48 Register Information (MA[7:0] = 30

) ............................................................. 178

Table 164 — MR48 Definition ...................................................................................................... 178

Table 165 — MR49 Register Information (MA[7:0] = 31

) ............................................................. 178

Table 166 — MR49 Definition ...................................................................................................... 178

Table 167 — MR50 Register Information (MA[7:0] = 32

) ............................................................. 178

Table 168 — MR50 Definition ...................................................................................................... 178

Table 169 — MR51 Register Information (MA[7:0] = 33

) ............................................................. 178

Table 170 — MR51 Definition ...................................................................................................... 178

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