CMX910芯片技术详解：AIS基带处理器

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"CMX910是一款专用于AIS（自动识别系统）的半双工调制解调芯片，提供了高效能的基带信号处理功能。该芯片具备GM(F)SK、FSK和DSC等多种调制能力，并集成了I和Q射频接口，适用于低功耗（3.0至3.6V）操作。其优化的同频和邻频性能使其在信号处理方面表现出色。CMX910采用紧凑型的64引脚LQFP或无引脚VQFN封装，提供灵活的信号通道设计，可以同时处理两个接收通道和一个发射通道，并可选配FSK接口。此外，它还带有辅助ADC和DAC功能，包括5个10位DAC和5输入MUX的10位ADC。该芯片支持AIS数据的格式化和原始数据模式，适用于海上安全的AIS设备，如AIS类A或B应答器以及仅接收的AIS模块。通过C-BUS串行接口和扩展端口，可以实现设备的扩展和控制。CMX910内含的电路包括HDLC/NRZI编解码器、消息缓冲区、GMSK/FSK解调器和编码器，以及辅助ADC和DAC，还有设备使能端口、FSK重定时（外部）、复位和电源控制功能，以及插槽和样本计数器，具有UTC时间接口。" 详细说明： 1. 调制解调能力：CMX910芯片支持半双工的GM(F)SK、FSK和DSC调制方式，这使得它能够处理各种无线通信标准，尤其适合AIS应用。 2. I和Q射频接口：I和Q射频接口是数字信号处理的基础，允许芯片进行复杂的调制和解调操作，提高了通信的效率和质量。 3. 低功耗运行：能够在3.0至3.6V的电压范围内工作，这使得CMX910适合电池供电或对能耗敏感的应用场景。 4. 高性能信号处理：芯片设计优化了同频道和相邻频道的性能，确保在复杂的无线环境中仍能保持良好的通信效果。 5. 封装形式：64引脚LQFP和无引脚VQFN两种封装选择，兼顾小型化和引脚数量的需求。 6. 灵活的信号通道：可以同时处理两个接收通道和一个发射通道，适应多任务并行处理，而可选的FSK接口增加了通信协议的兼容性。 7. 辅助ADC和DAC：5个10位的DAC和5输入MUX的10位ADC，用于提供额外的数据转换功能，增强了芯片的灵活性。 8. AIS支持：专门针对AIS系统设计，支持格式化和原始数据模式，适用于船舶安全通信，包括类A和类B的AIS应答器。 9. C-BUS串行接口：通过C-BUS接口，可以与外部设备连接，扩展功能并进行控制，便于系统集成。 10. 硬件控制功能：包含设备使能端口、FSK重定时、复位和电源控制，确保系统的稳定性和可靠性。 11. 计时接口：插槽和样本计数器结合UTC时间接口，确保精确的时序同步，这对于实时通信至关重要。 12. 应用领域：除了AIS系统，CMX910还可以用于支持CSTDMA（载波感应信道接入）操作的其他无线通信系统，如仅接收的AIS模块。这款芯片的设计考虑了多种通信需求，提供了全面的硬件和软件支持，使得基于AIS的无线通信系统能够高效、可靠地运行。

AIS Baseband Processor CMX910

Table 1 Summary of C-BUS Registers

C-BUS register name Addr R/W/

Cmd

Size C-BUS register name Addr R/W/

Cmd

Size

Reset and power control FSK Interface

General_Reset $01 Cmd - FSK_FIFO

(DS)

$50 R 8

Clock_Control $02 W 8 FSK_FIFO_Threshold $51 W 8

Slot and Sample Timer FSK_Status $52 R 16

Slot_Sample_Control $10 W 8 FSK_Control $53 W 8

Slot_Sample_Count $11 R 32 Auxiliary ADC

Sleep_Sample $12 W 16 ADC0 $60 R 16

Wakeup_Sample $13 W 16 ADC1 $61 R 16

Slot_Sample_UTC1PPS $14 R 32 ADC2 $62 R 16

Slot_Nudge $15 W 16 ADC3 $63 R 16

Sample_Nudge $16 W 16 ADC4 $64 R 16

Nudge_Trigger $17 W 16 ADC_Control1 $65 W 8

Max_Auto_Nudge $18 W 16 ADC_Control2 $66 W 8

Transmit Channel ADC_Status $67 R 8

Tx_FIFO

(DS)

$20 W 8 ADC_Convert $68 Cmd -

Tx_FIFO_Threshold $21 W 8 Auxiliary DACs

Tx_Status $22 R 16 DAC0 $70 W 16

Tx_Slot $23 W 16 DAC1 $71 W 16

Tx_Bits $24 W 16 DAC2 $72 W 16

Tx_Control $25 W 16 DAC2 $73 W 16

CSTDMA_Threshold $26 W 16 DAC4 $74 W 16

Receive Channel 1 DAC_Control $75 W 8

Rx1_FIFO

(DS)

$30 R 8 DAC0_Rampup $76 Cmd -

Rx1_FIFO_Threshold $31 W 8 DAC0_Rampdown $77 Cmd -

Rx1_Status $32 R 16 DAC0_Timestep $78 W 8

Rx1_Slot $33 R 16 DAC_RAM_Load

(DS)

$79 W 16

Rx1_Sample $34 R 16 Interrupts

Rx1_Bytes $35 R 16 Interrupt $80 R 16

Rx1_Control $36 W 8 Interrupt_Enable $81 W 16

Rx1_FreqErr $37 R 16 Device Enable Port

Rx1_RSSI $38 R 16 ENAB $90 W 8

Receive Channel 2 ENAB_Mask $91 W 8

Rx2_FIFO

(DS)

$40 R 8 ENAB_Invert $92 W 8

Rx2_FIFO_Threshold $41 W 8 C-BUS Expansion Port

Rx2_Status $42 R 16 CBUS_Expand $A0 W 8

Rx2_Slot $43 R 16 Special Command Interface

Rx2_Sample $44 R 16 SPC_In0 $B0 W 16

Rx2_Bytes $45 R 16 SPC_In1 $B1 W 16

Rx2_Control $46 W 8 SPC_Out0 $B2 R 16

Rx2_FreqErr $47 R 16 Special_Command $B4 W 8

Rx2_RSSI $48 R 16

(DS) - These registers are capable of data-streaming transactions.

Note: C-BUS addresses $F0 to $FE are allocated for production testing and should not be accessed in normal operation.

AIS Baseband Processor CMX910

5.3 Reset and Power Control

5.3.1 RESETN pin

The CMX910 is reset by taking RESETN low, which causes all internal clocks and bias currents to be

disabled and all C-BUS registers to be reset. To bring the CMX910 out of this quiescent state after

RESETN is pulled high, a stable clock signal must first be applied to the REFCLK input pin (any multiple

of 2.4MHz up to a maximum of 24MHz), then the Clock_Control register must be programmed with the

frequency of the applied REFCLK. A period of 10ms must then elapse to allow the CMX910 to initialise,

after which time the device is ready for operation. During operation the main Rx and Tx channel analogue

circuits and auxiliary ADC and DAC circuits will be powered up as required, depending on how the host

µC sets various C-BUS control and configuration registers.

5.3.2 General_Reset Command

General_Reset command (no data) C-BUS Address $01

This command disables all internal bias currents and resets all C-BUS registers except for CBUS_Expand

and Clock_Control. This means that if the CMX910’s internal clocks are running, they will remain running

when General_Reset is applied. After a General_Reset command, a period of 10ms must elapse to allow

the CMX910 to initialise before any further C-BUS operations are attempted.

5.3.3 Clock Control

The CMX910 can be put back into a low power state at any time by writing $00 to the Clock_Control

for CBUS_Expand. To subsequently bring the CMX910 out of this low power state requires the same

sequence of operations as if a RESETN pulse had been applied.

Clock_Control register: 8-bit write only. C-BUS Address $02

All bits cleared to 0 when RESETN pin asserted. Register contents are not affected by a General_Reset

command. This register can be written while the CMX910’s internal clocks are disabled.

Bit:

7 6 5 4 3 2 1 0

Reserved, set to 0000 REFCLK mult. factor

Clock_Control register b3-0: REFCLK Multiplication Factor

b3 b2 b1 b0

0 0 0 0 Internal clocks disabled, device held in low power mode

0 0 0 1 REFCLK = 2.4MHz

0 0 1 0 REFCLK = 4.8MHz

0 0 1 1 REFCLK = 7.2MHz

0 1 0 0 REFCLK = 9.6MHz

0 1 0 1 REFCLK = 12.0MHz

0 1 1 0 REFCLK = 14.4MHz

0 1 1 1 REFCLK = 16.8MHz

1 0 0 0 REFCLK = 19.2MHz

1 0 0 1 REFCLK = 21.6MHz

1 0 1 0 REFCLK = 24.0MHz

Codes 1011

to 1111

are reserved, do not use

AIS Baseband Processor CMX910

5.4 Slot and Sample Timer

The Slot and Sample Timer circuit contains two counters that are used to control and sequence

operations in the three main channels (Rx1, Rx2, Tx).

Slot_Sample_Count

Slot_Sample_UTC1PPS

Sample Counter

(11 bit)

A+B

Slot Counter

(12 bit)

A+B

kHz

Overflow

Sample_Nudge

Slot_Nudge

C-BUS

Nudge

Max_Auto_Nudge

Slot_Sample_Control

Nudge_Trigger

A=B

Comparator

Wakeup_Sample

A=B

Comparator

Sleep_Sample

A=B

Comparator

SLOTCLK

UTC1PPS

ctrl

Slot and Sample

Nudge Control Logic

Load

Sample_Count

Slot_Count

Figure 5 Slot and Sample Timer Circuit

The clock for the slot and sample counters is derived from the REFCLK input pin. The sample counter is

an 11 bit counter which increments at 48kHz, i.e. five times per AIS data bit, and is used to time various

Rx and Tx operations within a slot period. Since there are 256 bit periods per AIS slot, the sample counter

increments from 0 to 1279 before rolling over to 0. The slot counter is a 12 bit counter and is used to

count the slot number in an AIS frame, which lasts for a minute. It is incremented at the beginning of each

AIS slot period, i.e. when the sample counter rolls over. There are 37½ slots per second, resulting in 2250

slots per minute. Therefore the slot counter increments from 0 to 2249 before rolling over to 0. When

operating correctly, the slot counter rollover should be aligned to the start of the UTC minute. The current

value of the slot and sample counters are available to the µC by reading the Slot_Sample_Count register.

The CMX910 produces a pulse on its SLOTCLKN output pin during the first sample period within each

slot, this can be used as general timing reference by the µC.

Each pulse is active low and lasts for

approximately 20.83 µs, and the pulses repeat at 37.5Hz. The signal appearing on the SLOTCLKN pin

can be configured to be open-drain pull-down or have active pull-up and pull-down drivers.

When the CMX910 comes out of reset the slot and sample counters will be free running but not

synchronised to anything. The µC must synchronise them to an appropriate timing source, either UTC

(direct or indirect) or to an appropriate base station as required by Recommendation ITU-R M1371-1.

Once initial synchronisation has been established, occasional minor adjustments, or “nudges”, to the

sample counter must be made to keep it locked to the chosen timing source – this compensates for any

slight drift caused by inaccuracy in the REFCLK frequency. Nudge values can be calculated and applied

directly by the µC in a software control loop (“manual nudge”,

section 5.4.1). Alternatively, the CMX910

can be configured into certain “auto nudge” modes to establish initial synchronisation and subsequent

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