Altera FPGA SDI MegaCore Function User Guide v12.1

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"FPGA IP core SDI ug_sdi-12-1.pdf 是由Altera公司提供的关于Serial Digital Interface (SDI) MegaCore功能的用户指南，适用于Quartus II软件版本12.1。这份文档在2013年2月更新，主要涵盖了与SDI相关的详细设计信息和技术规格。" 正文: Serial Digital Interface (SDI) 是一种广泛应用于视频和音频广播领域的数字接口标准，用于无压缩高质量视频信号的传输。在FPGA (Field-Programmable Gate Array) 领域，Altera公司的SDI MegaCore功能提供了实现SDI接口的IP核，允许设计者在他们的FPGA设计中集成SDI输入和输出功能。在Quartus II版本12.1中，这个IP核支持了最新的SDI标准，包括HD-SDI（高清晰度SDI）和3G-SDI（3吉比特SDI），它们能处理从标清到高清甚至更高分辨率的视频信号。MegaCore是Altera提供的预验证IP解决方案之一，旨在简化和加速复杂设计的实现过程，尤其是涉及高速串行接口的设计。用户指南《SerialDigitalInterface(SDI)MegaCoreFunction》详细介绍了如何配置和使用SDI MegaCore。它可能包含了以下内容： 1. **功能概述**：介绍SDI MegaCore的功能特性，包括数据速率、同步机制、错误检测和恢复功能等。 2. **设计流程**：描述了如何在Quartus II环境中集成和配置SDI IP核，包括设置参数、接口连接和时序约束。 3. **接口规范**：详细解释了SDI接口的电气特性，如差分信号传输、阻抗匹配和信号完整性考虑。 4. **时钟管理**：讨论了与SDI传输相关的时钟要求，包括主时钟、数据恢复和锁相环路（PLL）配置。 5. **错误处理**：描述了如何处理传输过程中可能出现的错误，如帧丢失、同步丢失和数据错误。 6. **设计示例**：提供实际设计案例，展示如何将SDI IP核应用于具体的应用场景，例如视频接收器或发送器。 7. **调试与验证**：指导用户如何使用Quartus II工具进行IP核的仿真和硬件测试，以确保其正确工作。 8. **技术支持与更新**：提到了获取Altera官方技术支持的途径，以及文档和IP核的最新更新信息。 Altera公司强调，虽然他们对半导体产品的性能按照当前规格提供保证，但保留随时更改产品和服务的权利，而不会提前通知。用户在应用这些信息、产品或服务时，应自行承担风险，除非另有书面协议明确说明。这份文档是针对FPGA设计者的一份宝贵的参考资料，它详细阐述了如何在Quartus II 12.1环境下利用SDI MegaCore IP核实现高效的SDI接口设计，有助于提升视频处理应用的开发效率和性能。

2–2 Chapter 2: Getting Started

Design Flow

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation

User Guide

1. Create a custom variation of the SDI MegaCore function.

2. Implement the rest of your design using the design entry method of your choice.

3. Use the IP functional simulation model to verify the operation of your design.

f For more information on IP functional simulation models, refer to the

Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook.

Figure 2–1. Directory Structure

Contains the Altera MegaCore IP Library and third-party IP cores.

common

Contains shared components.

sdi

Contains the SDI MegaCore function files.

lib

Contains encrypted lower-level design files and other support files.

<path>

Installation directory.

simulation

Contains simulation files.

hdsdi_3g

Contains the HD-SDI 3 Gbps simulation files.

testbench

Contains the testbench files.

quartus

Contains the Quartus II NativeLink project.

pattern_gen

Contains the pattern generator files for the testbench.

testbench

Contains the testbench files.

quartus

Contains the Quartus II NativeLink project.

pattern_gen

Contains the pattern generator files for the testbench.

hdsdi_dual_link

Contains the HD-SDI dual link simulation files.

testbench

Contains the testbench files.

modelsim

Contains the ModelSim simulation files.

quartus

Contains the Quartus II NativeLink project.

pattern_gen

Contains the pattern generator files for the testbench.

hdsdi

Contains the HD-SDI simulation files.

altera

Contains the Altera MegaCore IP Library.

example

Contains design examples.

s2gx_tr

Contains a design example for Stratix II GX, see AN 339: Serial

Digital Interface Demonstration for Stratix II GX Devices.

a2gx_tr

Contains a design example for Arria II GX.

Chapter 2: Getting Started 2–3

SDI Walkthrough

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

4. Use the Quartus II software to compile your design.

1 You can also generate an OpenCore Plus time-limited programming file,

which you can use to verify the operation of your design in hardware.

5. Purchase a license for the SDI MegaCore function.

After you have purchased a license for the SDI MegaCore function, follow these

additional steps:

1. Set up licensing.

2. Generate a programming file for the Altera device or devices on your board.

3. Program the Altera device or devices with the completed design.

SDI Walkthrough

This walkthrough explains how to create an SDI design using the MegaWizard

Plug-In Manager and the Quartus II software. After you generate a custom variation

of the SDI MegaCore function, you can incorporate it into your overall project.

1 You can alternatively use the IP Advisor to help start your SDI MegaCore design. On

the Quartus II Tools menu, point to Advisors, and then click IP Advisor. The IP

Advisor guides you through a series of recommendations for selecting,

parameterizing, evaluating, and instantiating an SDI MegaCore function into your

design. It then guides you through a complete Quartus II compilation of your project.

This walkthrough requires the following steps:

1. “Creating a New Quartus II Project”

2. “Launching MegaWizard Plug-In Manager”

3. “Parameterizing”

4. “Setting Up Simulation”

5. “Generating Files”

Creating a New Quartus II Project

You must create a new Quartus II project with the New Project Wizard, which

specifies the working directory for the project, assigns the project name, and

designates the name of the top-level design entity. To create a new project, follow

these steps:

1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run

the Quartus II software. Alternatively, you can use the Quartus II Web Edition

software.

2. On the File menu, click New Project Wizard.

3. Click Next in the New Project Wizard: Introduction page (the introduction page

does not display if you turned it off previously).

2–4 Chapter 2: Getting Started

SDI Walkthrough

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation

User Guide

4. In the New Project Wizard: Directory, Name, Top-Level Entity page, enter the

following information:

a. Specify the working directory for your project. For example, this walkthrough

uses the c:\altera\projects\sdi_project directory.

1 The Quartus II software automatically specifies a top-level design entity

that has the same name as the project. This walkthrough assumes that the

names are the same.

b. Specify the name of the project. This walkthrough uses project for the project

name.

5. Click Next to close this page and display the New Project Wizard: Add Files page.

1 When you specify a directory that does not already exist, a message

prompts you to create a specified directory. Click Yes to create the directory.

6. If you installed the MegaCore IP Library in a different directory from where you

installed the Quartus II software, you must add the user libraries:

a. Click User Libraries.

b. Type <path>

\ip

into the Library name field, where <path> is the directory in

which you installed the SDI.

c. Click Add to add the path to the Quartus II project.

d. Click OK to save the library path in the project.

7. Click Next to close this page and display the New Project Wizard: Family &

Device Settings page.

8. On the New Project Wizard: Family & Device Settings page, choose the target

device family in the Family list.

9. The remaining pages in the New Project Wizard are optional. Click Finish to

complete the Quartus II project.

Launching MegaWizard Plug-In Manager

To launch the MegaWizard Plug-In Manager in the Quartus II software, follow these

steps:

1. On the Tools menu, click MegaWizard Plug-In Manager.

1 For more information about how to use the MegaWizard Plug-In Manager,

refer to Quartus II Help.

2. Specify that you want to create a new custom megafunction variation and click

Next.

3. Expand the Interfaces > SDI folder and click SDI <version>.

4. Select the output file type for your design; the wizard supports VHDL and Verilog

HDL.

Chapter 2: Getting Started 2–5

SDI Walkthrough

February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function

User Guide

5. The MegaWizard Plug-In Manager shows the project path that you specified in the

New Project Wizard. Append a variation name for the MegaCore function output

files <project path>\<variation name>.

6. Click Next to display the Parameter Settings page for the SDI MegaCore function.

1 You can change the page that the MegaWizard Plug-In Manager displays by

clicking Next or Back at the bottom of the dialog box. You can move

directly to a named page by clicking the Parameter Settings, EDA, or

Summary tab.

Also, you can directly display individual parameter settings by clicking on

the Protocol Options, Transceiver Options, or Receiver/Transmitter

Options tab.

Parameterizing

To parameterize your MegaCore function, follow these steps:

1. Select the video standard. Some of the standards may be grayed out, because they

are not supported on the currently selected device family.

2. Select Bidirectional, Receiver, or Tr ansmi tt er interface direction.

3. Click the Transceiver Options tab.

4. Under Transceiver and Protocol, click Generate transceiver and protocol blocks.

5. For SD-SDI only, turn on Use soft logic for transceiver to implement the

transceiver in logic, rather than using Stratix GX, Stratix II GX or Stratix IV GX

transceivers.

6. Select the starting channel number.

7. Turn on Use PLL reconfiguration for transceiver dynamic reconfiguration if you

select an EP4CGX110 or EP4CGX150 device for Cyclone IV GX using dual and

triple standards. You may turn on this option for other Cyclone IV GX devices but

it is not recommended.

8. Turn on Enable TX PLL select for 1/1.000 and 1/1.001 data rate reconfiguration if

your design requires two serial input clocks to the TX block.

1 This feature is only available for the Arria II, Stratix IV GX, and

HardCopy IV GX device families.

9. Click the Receiver/Transmitter Options tab.

10. Turn on the required receiver options.

11. Turn on the required transmitter options.

12. Click Next (or the EDA tab) to display the EDA page.

f For more information about parameters, refer to “Parameters” on page 3–56 and, for

more information about the protocol options, refer to Table 3–20 on page 3–56.

For more information about the transceiver options, refer to Table 3–21 on page 3–56.

For more information about the receiver/transmitter options, refer to Table 3–22 on

page 3–57.

2–6 Chapter 2: Getting Started

SDI Walkthrough

Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation

User Guide

Setting Up Simulation

An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model

produced by the Quartus II software. The model allows for fast functional simulation

of IP using industry-standard VHDL and Verilog HDL simulators.

c You may only use these models for simulation and expressly not for synthesis or any

other purposes. Using these models for synthesis creates a nonfunctional design.

To generate an IP functional simulation model for your MegaCore function, follow

these steps:

1. Turn on Generate simulation model.

2. Some third-party synthesis tools can use a netlist that contains only the structure

of the MegaCore function, but not detailed logic, to optimize performance of the

design that contains the MegaCore function. If your synthesis tool supports this

feature, turn on Generate netlist.

3. Click Next (or the Summary tab) to display the Summary page.

Generating Files

You can use the check boxes on the Summary page to enable or disable the generation

of specified files. A gray checkmark indicates a file that is automatically generated; a

red checkmark indicates an optional file.

You can click Back to display the previous page, or click Parameters Settings, EDA,

or Summary, to change any of the MegaWizard options.

To generate the files, follow these steps:

1. Turn on the files you wish to generate.

1 At this stage, you can still click Back to display any of the other pages in the

MegaWizard Plug-In Manager to change any of the parameters.

2. To generate the specified files and close the MegaWizard Plug-In Manager, click

Finish.

1 The generation phase may take several minutes to complete.

1 The Quartus II IP File (.qip) is a file generated by the parameter editor, and

contains information about the generated IP core. You are prompted to add

this .qip file to the current Quartus II project at the time of file generation.

In most cases, the .qip file contains all of the necessary assignments and

information required to process the core or system in the Quartus II

compiler. Generally, a single .qip file is generated for each MegaCore

function or system in the Quartus II compiler.

3. Click Exit to close the Generation window.

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