Contents — Continued
J.10. Barrier Synchronization
............................................................................................. 279
Appendix K Formal Specification of the Memory Model
......................... 281
K.1. Notation
............................................................................................................................... 281
K.2. Total Store Ordering
..................................................................................................... 283
K.3. Partial Store Ordering
.................................................................................................. 285
K.4. FLUSH: Synchronizing Instruction Fetches with Memory
Operations
........................................................................................................................... 287
Appendix L Implementation Characteristics
....................................................... 289
L.1. PSR impl and ver Values
............................................................................................ 289
L.2. FSR ver Values
................................................................................................................ 290
L.3. Characteristics of Existing Implementations
.................................................. 291
Unimplemented Instructions
.................................................................................. 292
FLUSH Instruction
....................................................................................................... 292
Integer Deferred-Trap Queue
................................................................................. 293
Floating-point Deferred-Trap Queue (FQ) and STDFQ
Instruction
......................................................................................................................... 293
FSR_nonstandard_fp
.................................................................................................. 293
FPU Exceptions
............................................................................................................. 293
Trap Model and Trap Types
................................................................................... 294
Memory Model and STBAR Instruction
......................................................... 294
Ancillary State Registers
.......................................................................................... 294
Width of Load/Store Effective Address
........................................................... 294
Number of Windows
................................................................................................... 294
Instruction Timing
........................................................................................................ 295
Appendix M Instruction Set Summary
..................................................................... 297
Appendix N SPARC IEEE 754 Implementation
Recommendations
......................................................................................... 299
N.1. Misaligned floating-point data registers
............................................................ 299
N.2. Reading an empty FQ
.................................................................................................. 299
N.3. Traps inhibit results
....................................................................................................... 299
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