Altera Cyclone器件Timequest实例详解（QII53018-11.1.0）

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本文档是关于TimeQuest的实例教程，主要针对Altera公司的FPGA（Field-Programmable Gate Array）器件，如Cyclone、Arria、MAX、MEGAcore、Nios II等，使用的是Quartus II版本11.1.0。时间quest是一款由Altera公司提供的设计工具，用于硬件描述语言（HDL）的设计、仿真和验证，特别适用于时序逻辑设计。在Quartus II Handbook Volume 3: Verification部分，作者详细介绍了如何在实际项目中运用TimeQuest进行高级综合、时序分析、逻辑综合优化以及一致性检查等。这个版本的文档更新于2011年11月，强调了 Altera对产品质量的保证，按照标准保修政策提供支持，但同时也提醒用户产品和服务可能会有所变更，且建议用户在依赖任何公开信息或下单前，应获取最新的器件规格。在使用TimeQuest实例时，可能会涉及以下关键知识点： 1. 高级综合：学习如何使用高级综合技术，如约束文件（UCF）管理时序、电源和布局布线，以提升设计的性能和效率。 2. 时序分析：掌握如何进行时序分析，包括设置时钟树、信号路径延迟测量、关键路径识别，以确保设计满足时序要求。 3. 逻辑综合优化：理解如何应用优化选项，如层次综合、自动资源分配和功耗优化，以减小芯片面积并提高功耗效率。 4. 一致性检查：学习如何使用一致性检查工具，确保设计在不同的目标架构上表现一致，并避免潜在的设计冲突。 5. IP核集成：如果文档中包含特定的IP核（知识产权）实例，将涉及如何正确配置和集成这些预设计的模块到主设计中。 6. Quartus II环境：熟悉Quartus II IDE的工作流程，包括创建项目、添加源代码、设置设计规则和运行仿真。 7. 最佳实践：文档可能还包含了设计和验证过程中的最佳实践，如使用仿真模型、测试benches以及遵循行业标准和规范。 8. 版本更新和兼容性：由于文档是针对11.1.0版本，了解后续版本的改进和可能存在的向下兼容问题也非常重要。本篇文档是Altera FPGA设计人员的宝贵参考资料，通过深入理解和应用TimeQuest实例，用户可以提升设计质量和效率，同时确保遵循行业标准和Altera的产品策略。

7–12 Chapter 7: The Quartus II TimeQuest Timing Analyzer

Design Constraints: An Example

Quartus II Handbook Version 11.1 November 2011 Altera Corporation

Volume 3: Verification

Example 7–5 shows an SDC file containing basic constraints for the circuit in

Figure 7–4.

The SDC file shown in Example 7–5 contains the following basic constraints you

should inlculde for most designs:

■ Definitions of

clockone

and

clocktwo

as base clocks, and assignment of those

settings to nodes in the design.

■ Definition of a generated clock and assignment of those settings to the output of

the PLL in the design. Note in the example that you can achieve this constraint by

initially running timing analysis with the

derive_pll_clocks

command, and then

adding the specific derived clock constraints from the TimeQuest console to your

SDC file.

■ Derivation of clock uncertainty.

Example 7–5. Example Basic SDC Constraints

# Create clock constraints

create_clock -name clockone -period 10.000 [get_ports {clk1}]

create_clock -name clocktwo -period 10.000 [get_ports {clk2}]

# derive_pll_clocks, then copy the derivations themselves

# as constraints

# analyzed once with derive_pll_clocks, to get the following clock

# settings for altpll0

create_generated_clock \

-source {altpll0|altpll_component|auto_generated|pll1|inclk[0]} \

-multiply_by 2 -phase 180.00 \

-duty_cycle 50.00 \

-name {altpll0|altpll_component|auto_generated|pll1|clk[0]} \

{altpll0|altpll_component|auto_generated|pll1|clk[0]}

# derive clock uncertainty

derive_clock_uncertainty

# Specify that clockone and clocktwo are unrelated by assinging

# them to seperate exclusive groups

set_clock_groups \

-exclusive \

-group [get_clocks {clockone}] \

-group [get_clocks {clocktwo \

altpll0|altpll_component|auto_generated|pll1|clk[0]}]

# set input and output delays

set_input_delay -clock { clockone } -max 4 [get_ports {data1}]

set_input_delay -clock { clockone } -min -1 [get_ports {data1}]

set_input_delay -clock { clockone } -max 4 [get_ports {data2}]

set_input_delay -clock { clockone } -min -1 [get_ports {data2}]

set_output_delay \

-clock { altpll0|altpll_component|auto_generated|pll1|clk[0] } \

-max -3 [get_ports {dataout}]

set_output_delay \

-clock { altpll0|altpll_component|auto_generated|pll1|clk[0] } \

-min 6 [get_ports {dataout}]

Chapter 7: The Quartus II TimeQuest Timing Analyzer 7–13

Creating Clocks and Clock Constraints

November 2011 Altera Corporation Quartus II Handbook Version 11.1

Volume 3: Verification

■ Specification of two mutually exclusive clock groups, one containing

clockone

and the other containing

clocktwo

. This overrides the default analysis of all clocks

in the design as related to each other. For more information about exclusive clock

groups, refer to “Exclusive Clock Groups” on page 7–20.

■ Specification of input and output delays for the design.

The following sections describe each of these constraint types in greater detail.

Creating Clocks and Clock Constraints

To ensure accurate static timing analysis results, you must specify all clocks and any

associated clock characteristics in your design. The TimeQuest analyzer supports SDC

commands that accommodate various clocking schemes and clock characteristics.

The TimeQuest analyzer supports the following types of clocks:

■ Base clocks

■ Virtual clocks

■ Multifrequency clocks

■ Generated clocks

Clocks are used to specify register-to-register requirements for synchronous transfers

and guide the Fitter optimization algorithms to achieve the best possible placement

for your design.

Specify clock constraints first in Synopsys Design Constraint Files (.sdc) because other

constraints may reference previously defined clocks. The TimeQuest analyzer reads

SDC constraints and exceptions from top to bottom in the file.

Creating Base Clocks

Base clocks are the primary input clocks to the FPGA. Unlike clocks from

phase-locked loops (PLLs) that are generated within the FPGA, base clocks are

usually generated by off-chip oscillators or forwarded from an external device. Define

base clocks first because generated clocks and other constraints often reference base

clocks.

To create clock settings for the signal from any register, port, or pin, use the

create_clock

command. You can create each clock with unique characteristics.

Clocks defined with the

create_clock

command have a default source latency value

of zero. The TimeQuest analyzer automatically computes the clock’s network latency

for non-virtual clocks.

Example 7–6 shows how to create a 10 ns clock with a 50% duty cycle that is phase

shifted by 90 degrees applied to port

clk_sys

Example 7–6. 100MHz Shifted by 90 Degrees Clock Creation

create_clock -period 10 -waveform { 2.5 7.5 } [get_ports clk_sys]

7–14 Chapter 7: The Quartus II TimeQuest Timing Analyzer

Creating Clocks and Clock Constraints

Quartus II Handbook Version 11.1 November 2011 Altera Corporation

Volume 3: Verification

Use the

create_clock

command to constrain all primary input clocks. The target for

the

create_clock

command is usually an FPGA device pin. To specify the FPGA

device pin as the target, use the

get_ports

command. Example 7–7 shows how to

specify a 100-MHz requirement on a

clk_sys

input clock port.

You can apply multiple clocks on the same clock node with the

-add

option.

Example 7–8 shows how to specify that two oscillators drive the same clock port on

the FPGA.

h For more information about the

create_clock

and

get_ports

commands—including

full syntax information, options, and example usage—refer to create_clock and

get_ports in Quartus II Help.

Creating Virtual Clocks

A virtual clock is a clock that does not have a real source in the design or that does not

interact directly with the design. To create virtual clocks, use the

create_clock

command with no value specified for the <targets> option. For example, if a clock

feeds only an external device’s clock port and not a clock port in the design, and the

external device connects to a port in the design, the clock is considered a virtual clock.

Use virtual clocks with the

set_input_delay

and

set_output_delay

commands when

you use the

derive_clock_uncertainty

command for your design. The TimeQuest

analyzer uses virtual clocks to calculate clock uncertainty separately for I/O interfaces

and internal register-to-register paths.

When an FPGA interfaces with an external device, and both the FPGA and external

device have different clock sources, you should model the clock source for the

external device with a virtual clock.

h For more information about the

set_input_delay

set_output_delay

, and

derive_clock_uncertainty

commands—including full syntax information, options,

and example usage—refer to set_input_delay, set_output_delay, and

derive_clock_uncertainty in Quartus II Help.

You can create virtual clocks with the

create_clock

command, with no targets

specified. Example 7–9 shows how to create a 10 ns virtual clock.

Example 7–7. create_clock Command

create_clock -period 10 -name clk_sys [get_ports clk_sys]

Example 7–8. Two Oscillators Driving the Same Clock Port

create_clock -period 10 -name clk_100 [get_ports clk_sys]

create_clock -period 5 -name clk_200 [get_ports clk_sys] -add

Example 7–9. Create Virtual Clock

create_clock -period 10 -name my_virt_clk

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