TMS320VC55x DSP 数据手册：Fixed-Point Digital Signal Processor

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"TMS320VC55x系列固定点数字信号处理器数据手册，生产数据信息截至出版日期，TI保留随时对产品和服务进行修改、增强、改进或其他更改的权利，所有产品均按订单确认时的销售条款和条件出售。TI对其硬件产品的性能按照销售时适用的规格提供标准保修，使用测试和其他质量控制技术来支持此保修。" 《TMS320VC55x数据手册》是针对德州仪器（Texas Instruments, TI）开发的TMS320VC55x系列固定点数字信号处理器（DSP）的重要参考资料。该系列芯片主要用于高性能、低功耗的应用，如通信、音频处理、图像处理和工业自动化等领域。以下是手册中可能包含的关键知识点： 1. **处理器架构**：TMS320VC55x系列基于高效的VLIW（Very Long Instruction Word）架构，能够在单个时钟周期内执行多个操作，提高了处理效率。 2. **指令集**：手册会详细介绍该系列DSP的指令集，包括基本操作、浮点运算、乘法累加（MAC）、分支和循环控制等。 3. **存储器组织**：手册会描述处理器的内部存储结构，包括数据存储器（Data Memory）、程序存储器（Program Memory）以及各种寄存器的布局和功能。 4. **外围接口和外设**：TMS320VC55x可能包含多种外设接口，如串行端口、定时器、DMA控制器等，这些外设的使用方法和配置在手册中会详述。 5. **电源管理**：手册会涵盖芯片的电源管理特性，如动态电压和频率调整（DVFS），以适应不同应用的功耗需求。 6. **开发工具和软件支持**：手册可能提及TI提供的开发工具链，如编译器、调试器和实时操作系统（RTOS）支持。 7. **硬件设计和应用示例**：对于系统设计者，手册会提供电路设计指导，包括封装信息、引脚配置、电气特性以及应用电路示例。 8. **性能指标**：手册会列出处理器的性能指标，如工作频率、计算能力、功耗等，以帮助设计者评估其在特定应用中的表现。 9. **错误检测和纠正**：手册可能包括错误检测和纠正机制，如奇偶校验位、ECC等，以提高系统可靠性。 10. **标准保修和责任声明**：TI在手册中明确指出，产品性能符合销售时的标准规格，并提供保修服务。但同时提醒客户在下单前验证信息的最新性和完整性。 TMS320VC55x数据手册是开发者和工程师理解、设计和优化基于该处理器系统的核心资源，它提供了全面的技术细节和操作指南，以确保高效、稳定地利用该DSP平台进行系统开发。

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Introduction

April 2001 − Revised January 2004SPRS163F

Table 2−2. Pin Assignments for the PGE Package

PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME

1 V

37 V

73 V

109 RDV

2 PU 38 A13 74 D12 110 RCV

3 DP 39 A12 75 D13 111 RTCINX2

4 DN 40 A11 76 D14 112 RTCINX1

5 USBV

41 CV

77 D15 113 V

6 GPIO7 42 A10 78 CV

114 V

7 V

43 A9 79 EMU0 115 V

8 DV

44 A8 80 EMU1/OFF 116 S23

9 GPIO2 45 V

81 TDO 117 S25

10 GPIO1 46 A7 82 TDI 118 CV

11 V

47 A6 83 CV

119 S24

12 GPIO0 48 A5 84 TRST 120 S21

13 X2/CLKIN 49 DV

85 TCK 121 S22

14 X1 50 A4 86 TMS 122 V

15 CLKOUT 51 A3 87 RV

123 S20

16 C0 52 A2 88 DV

124 S13

17 C1 53 RV

89 SDA 125 S15

18 CV

54 A1 90 SCL 126 DV

19 C2 55 A0 91 RESET 127 S14

20 C3 56 DV

92 V

128 S11

21 C4 57 D0 93 INT0 129 S12

22 C5 58 D1 94 INT1 130 S10

23 C6 59 D2 95 CV

131 DX0

24 DV

60 V

96 INT2 132 CV

25 C7 61 D3 97 INT3 133 FSX0

26 C8 62 D4 98 DV

134 CLKX0

27 C9 63 D5 99 INT4 135 DR0

28 C11 64 V

100 V

136 FSR0

29 CV

65 D6 101 XF 137 CLKR0

30 RV

66 D7 102 V

138 V

31 C14 67 D8 103 ADV

139 DV

32 C12 68 CV

104 ADV

140 TIN/TOUT0

33 V

69 D9 105 AIN0 141 GPIO6

34 C10 70 D10 106 AIN1 142 GPIO4

35 C13 71 D11 107 AV

143 GPIO3

36 V

72 DV

108 AV

144 V

Introduction

April 2001 − Revised January 2004 SPRS163F

2.3 Signal Descriptions

Table 2−3 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for pin

locations based on package type.

Table 2−3. Signal Descriptions

TERMINAL

NAME

MULTIPLEXED

SIGNAL NAME

I/O/Z

†

FUNCTION BK

‡

RESET

CONDITION

PARALLEL BUS

A[13:0] I/O/Z

A subset of the parallel address bus A13−A0 of the C55x DSP core

bonded to external pins. These pins serve in one of three functions: HPI

address bus (HPI.HA[13:0]), EMIF address bus (EMIF.A[13:0]), or

general-purpose I/O (GPIO.A[13:0]). The initial state of these pins

depends on the GPIO0 pin. See Section 3.5.1 for more information.

The address bus has a bus holder feature that eliminates passive

component requirement and the power dissipation associated with them.

The bus holders keep the address bus at the previous logic level when the

bus goes into a high-impedance state.

GPIO0 = 1:

HPI.HA[13:0] I

HPI address bus. HPI.HA[13:0] is selected when the Parallel Port Mode bit

field of the External Bus Selection Register is 10. This setting enables the

HPI in non-multiplexed mode.

HPI.HA[13:0] provides DSP internal memory access to host. In

non-multiplexed mode, these signals are driven by an external host as

address lines.

GPIO0 = 1:

Output,

EMIF.A[13:0]

GPIO0 = 0:

EMIF.A[13:0] O/Z

EMIF address bus. EMIF.A[13:0] is selected when the Parallel Port Mode

bit field of the External Bus Selection Register is 01. This setting enables

the full EMIF mode and the EMIF drives the parallel port address bus. The

internal A[14] address is exclusive-ORed with internal A[0] address and

the result is routed to the A[0] pin.

Input,

HPI.HA[13:0]

GPIO.A[13:0] I/O/Z

General-purpose I/O address bus. GPIO.A[13:0] is selected when the

Parallel Port Mode bit field of the External Bus Selection Register is 11.

This setting enables the HPI in multiplexed mode with the Parallel Port

GPIO register controlling the parallel port address bus. GPIO is also

selected when the Parallel Port Mode bit field is 00, enabling the Data

EMIF mode.

A′[0]

(BGA only)

EMIF.A′[0] O/Z

EMIF address bus A′[0]. This pin is not multiplexed with EMIF.A[14] and is

used as the least significant external address pin on the BGA package.

Output

†

I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡

BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer

Introduction

April 2001 − Revised January 2004SPRS163F

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

RESET

CONDITION

‡

FUNCTIONI/O/Z

†

MULTIPLEXED

SIGNAL NAME

PARALLEL BUS (CONTINUED)

A[15:14]

(BGA only)

I/O/Z

A subset of the parallel address bus A15−A14 of the C55x DSP core

bonded to external pins. These pins serve in one of two functions: EMIF

address bus (EMIF.A[15:14]), or general-purpose I/O (GPIO.A[15:14]).

The initial state of these pins depends on the GPIO0 pin. See Section 3.5.1

for more information.

The address bus has a bus holder feature that eliminates passive

component requirement and the power dissipation associated with them.

The bus holders keep the address bus at the previous logic level when the

bus goes into a high-impedance state.

GPIO0 = 1:

Output,

EMIF.A[15:14]

EMIF.A[15:14] O/Z

EMIF address bus. EMIF.A[15:14] is selected when the Parallel Port Mode

bit field of the External Bus Selection Register is 01. This setting enables

the full EMIF mode and the EMIF drives the parallel port address bus.

GPIO0 = 0:

Input,

GPIO.A[15:14]

GPIO.A[15:14] I/O/Z

General-purpose I/O address bus. GPIO.A[15:14] is selected when the

Parallel Port Mode bit field of the External Bus Selection Register is 11.

This setting enables the HPI in multiplexed mode with the Parallel Port

GPIO register controlling the parallel port address bus. GPIO is also

selected when the Parallel Port Mode bit field is 00, enabling the Data

EMIF mode.

GPIO.A[15:14]

A[20:16]

(BGA only)

EMIF.A[20:16] O/Z

EMIF address bus. At reset, these address pins are set as output.

NOTE: These pins only function as EMIF address pins and they are not

multiplexed for any other function.

Output

D[15:0] I/O/Z

A subset of the parallel bidirectional data bus D31−D0 of the C55x DSP

core. These pins serve in one of two functions: EMIF data bus

(EMIF.D[15:0]) or HPI data bus (HPI.HD[15:0]). The initial state of these

pins depends on the GPIO0 pin. See Section 3.5.1 for more information.

The data bus includes bus keepers to reduce the static power dissipation

caused by floating, unused pins. This eliminates the need for external bias

resistors on unused pins. When the data bus is not being driven by the

CPU, the bus keepers keep the pins at the logic level that was most

recently driven. (The data bus keepers are disabled at reset, and can be

enabled/disabled under software control.)

GPIO0 = 1:

Input,

EMIF.D[15:0]

GPIO0 = 0:

Input,

HPI.HD[15:0]

EMIF.D[15:0] I/O/Z

EMIF data bus. EMIF.D[15:0] is selected when the Parallel Port Mode bit

field of the External Bus Selection Register is 00 or 01.

HPI.HD[15:0]

HPI.HD[15:0] I/O/Z

HPI data bus. HPI.HD[15:0] is selected when the Parallel Port Mode bit

field of the External Bus Selection Register is 10 or 11.

†

I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡

BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer

Introduction

April 2001 − Revised January 2004 SPRS163F

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

RESET

CONDITION

‡

FUNCTIONI/O/Z

†

MULTIPLEXED

SIGNAL NAME

PARALLEL BUS (CONTINUED)

C0 I/O/Z

EMIF asynchronous memory read enable or general-purpose IO8. This

pin serves in one of two functions: EMIF asynchronous memory read

enable (EMIF.ARE) or general-purpose IO8 (GPIO8). The initial state of

this pin depends on the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.ARE

EMIF.ARE O/Z

Active-low EMIF asynchronous memory read enable. EMIF.ARE is

selected when the Parallel Port Mode bit field of the External Bus Selection

EMIF.ARE

GPIO0 = 0:

Input,

GPIO8 I/O/Z

General-purpose IO8. GPIO8 is selected when the Parallel Port Mode bit

field of the External Bus Selection Register is set to 10 or 11.

Input,

GPIO8

C1 O/Z

EMIF asynchronous memory output enable or HPI interrupt output. This

pin serves in one of two functions: EMIF asynchronous memory output

enable (EMIF.AOE) or HPI interrupt output (HPI.HINT). The initial state of

this pin depends on the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.AOE

EMIF.AOE O/Z

Active-low asynchronous memory output enable. EMIF.AOE is selected

when the Parallel Port Mode bit field of the External Bus Selection Register

is 00 or 01.

EMIF.AOE

GPIO0 = 0:

Output,

HPI.HINT O/Z

Active-low HPI interrupt output. HPI.HINT is selected when the Parallel

Port Mode bit field of the External Bus Selection Register is 10 or 11.

Output,

HPI.HINT

C2 I/O/Z

EMIF asynchronous memory write enable or HPI read/write. This pin

serves in one of two functions: EMIF asynchronous memory write enable

(EMIF.AWE) or HPI read/write (HPI.HR/W). The initial state of this pin

depends on the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.AWE

EMIF.AWE O/Z

Active-low EMIF asynchronous memory write enable. EMIF.AWE is

selected when the Parallel Port Mode bit field of the External Bus Selection

EMIF.AWE

GPIO0 = 0:

Input,

HPI.HR/W I

HPI read/write. HPI.HR/W is selected when the Parallel Port Mode bit field

of the External Bus Selection Register is 10 or 11. HPI.HR/W controls the

direction of the HPI transfer.

Input,

HPI.HR/W

C3 I/O/Z

EMIF data ready input or HPI ready output. This pin serves in one of two

functions: EMIF data ready input (EMIF.ARDY) or HPI ready output

(HPI.HRDY). The initial state of this pin depends on the GPIO0 pin. See

Section 3.5.1 for more information.

GPIO0 = 1:

Input,

EMIF.ARDY I

EMIF data ready input. Used to insert wait states for slow memories.

EMIF.ARDY is selected when the Parallel Port Mode bit field of the

External Bus Selection Register is 00 or 01.

NOTE: With the buskeeper being active after reset, a strong 2.2K pullup is

necessary on this signal.

Input,

EMIF.ARDY

GPIO0 = 0:

Output,

HPI.HRDY

HPI.HRDY O/Z

HPI ready output. HPI.HRDY is selected when the Parallel Port Mode bit

field of the External Bus Selection Register is 10 or 11.

†

I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡

BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer

Introduction

April 2001 − Revised January 2004SPRS163F

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

RESET

CONDITION

‡

FUNCTIONI/O/Z

†

MULTIPLEXED

SIGNAL NAME

PARALLEL BUS (CONTINUED)

C4 I/O/Z

EMIF chip select for memory space CE0 or general-purpose IO9. This pin

serves in one of two functions: EMIF chip select for memory space CE0

(EMIF.CE0) or general-purpose IO9 (GPIO9). The initial state of this pin

depends on the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.CE0

EMIF.CE0 O/Z

Active-low EMIF chip select for memory space CE0. EMIF.CE0 is selected

when the Parallel Port Mode bit field of the External Bus Selection Register

is set to 00 or 01.

EMIF.CE0

GPIO0 = 0:

Input,

GPIO9 I/O/Z

General-purpose IO9. GPIO9 is selected when the Parallel Port Mode bit

field of the External Bus Selection Register is set to 10 or 11.

Input,

GPIO9

C5 I/O/Z

EMIF chip select for memory space CE1 or general-purpose IO10. This pin

serves in one of two functions: EMIF chip-select for memory space CE1

(EMIF.CE1) or general-purpose IO10 (GPIO10). The initial state of this pin

depends on the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.CE1

EMIF.CE1 O/Z

Active-low EMIF chip select for memory space CE1. EMIF.CE1 is selected

when the Parallel Port Mode bit field of the External Bus Selection Register

is set to 00 or 01.

EMIF.CE1

GPIO0 = 0:

Input,

GPIO10 I/O/Z

General-purpose IO10. GPIO10 is selected when the Parallel Port Mode

bit field of the External Bus Selection Register is set to 10 or 11.

Input,

GPIO10

C6 I/O/Z

EMIF chip select for memory space CE2 or HPI control input 0. This pin

serves in one of two functions: EMIF chip-select for memory space CE2

(EMIF.CE2) or HPI control input 0 (HPI.HCNTL0). The initial state of this

pin depends on the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.CE2 O/Z

Active-low EMIF chip select for memory space CE2. EMIF.CE2 is selected

when the Parallel Port Mode bit field of the External Bus Selection Register

is set to 00 or 01.

Output,

EMIF.CE2

GPIO0 = 0:

HPI.HCNTL0 I

HPI control input 0. This pin, in conjunction with HPI.HCNTL1, selects a

host access to one of the three HPI registers. HPI.HCNTL0 is selected

when the Parallel Port Mode bit field of the External Bus Selection Register

is set to 10 or 11.

GPIO0 = 0:

Input,

HPI.HCNTL0

C7 I/O/Z

EMIF chip select for memory space CE3, general-purpose IO11, or HPI

control input 1. This pin serves in one of three functions: EMIF chip-select

for memory space CE3 (EMIF.CE3), general-purpose IO11 (GPIO11), or

HPI control input 1 (HPI.HCNTL1). The initial state of this pin depends on

the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.CE3 O/Z

Active-low EMIF chip select for memory space CE3. EMIF.CE3 is selected

when the Parallel Port Mode bit field is of the External Bus Selection

Output,

EMIF.CE3

GPIO0 = 0:

GPIO11 I/O/Z

General-purpose IO11. GPIO11 is selected when the Parallel Port Mode

bit field is set to 10.

GPIO0 = 0:

Input,

HPI.HCNTL1

HPI.HCNTL1 I

HPI control input 1. This pin, in conjunction with HPI.HCNTL0, selects a

host access to one of the three HPI registers. The HPI.HCNTL1 mode is

selected when the Parallel Port Mode bit field is set to 11.

HPI.HCNTL1

†

I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡

BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer

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