"ADRV9002数据手册:双窄带和宽带射频收发器技术支持和规格变更"

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Data Sheet ADRV9002

SPECIFICATIONS

analog.com Rev. 0 | 15 of 92

POWER SUPPLY SPECIFICATIONS

Table 5.

Parameter Min Typ Max Unit

SUPPLY CHARACTERISTICS

VDDA_1P0

Analog Supplies 0.975 1.0 1.025 V

VDD_1P0

Digital Supply 0.95 1.0 1.05 V

VDDA_1P3

Analog Supplies 1.267 1.3 1.33 V

VDDA_1P8 Analog Supplies 1.71 1.8 1.89 V

VDD_1P8

Digital Supply 1.71 1.8 1.89 V

VDDA_1P0 refers to all analog 1.0 V supplies that operate with the internal low dropout (LDO) regulator bypassed. The power domain that allows the internal LDO regulator

bypass includes VRFLO2_1P0, VRFLO1_1P0, VRX2LO_1P3, VRX1LO_1P3, VTX2LO_1P3, VCONV_1P3, and VTX1LO_1P3.

VDD_1P0 refers to all digital 1.0 V supplies including VDIG_1P0.

VDDA_1P3 refers to all analog 1.3 V supplies including VRFVCO2_1P3, VRFVCO1_1P3, VANA2_1P3, VANA1_1P3, VRX2LO_1P3, VCLKSYN_1P3, VRFSYN2_1P3,

VRFSYN1_1P3, VAUXSYN_1P3, VRX1LO_1P3, VTX2LO_1P3, VCLKVCO_1P3, VAUXVCO_1P3, VTX1LO_1P3, and VCONV_1P3.

VDD_1P8 refers to all digital 1.8 V supplies including VDIGIO_1P8.

CURRENT CONSUMPTION ESTIMATES (TYPICAL VALUES)

No external VDDA_1P0 1.0 V power domain is used in Table 6 to Table 11. In all following modes described, the ADRV9002 operates with

internal LDO regulators used to produce an on-chip, 1.0 V analog power domain.

Sleep Mode

Table 6. Digital Mobile Radio (DMR) CMOS SSI

ADRV9002 Mode Conditions

Supply (mA)

Total Average

Power (W)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

Receiver, Transmitter, Clock PLL, and LDO Regulator Powered

Down, Internal Microprocessor Active, CMOS SSI Interface Off,

DEV_CLK_OUT Off, and Auxiliary DACs Off

Not used 18.9 8.2 9.7 1.3 0.049

Receiver, Transmitter, Clock PLL, LDO Regulator, and Internal

Microprocessor Powered Down, CMOS SSI Interface Off,

DEV_CLK_OUT Off, and Auxiliary DACs Off

Not used 2.3 6.9 9.7 1.3 0.031

Table 7. Long-Term Evolution (LTE) Dual Transmitter and Dual Receiver LVDS SSI

ADRV9002 Mode Conditions

Supply (mA)

Total Average

Power (W)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

Receiver, Transmitter, Clock PLL, and LDO Regulator Powered Down,

Internal Microprocessor Active, LVDS SSI Interface Off, DEV_CLK_OUT

Off, and Auxiliary DACs Off

Not used 24.6 12.4 11.3 1.3 0.066

Receiver, Transmitter, Clock PLL, LDO Regulator, and Internal

Microprocessor Powered Down, LVDS SSI Interface Off, DEV_CLK_OUT

Off, and Auxiliary DACs Off

Not used 2.3 10.3 10.6 1.3 0.037

Data Sheet ADRV9002

SPECIFICATIONS

analog.com Rev. 0 | 16 of 92

TDD Operation

Table 8. DMR, 4× External LO, LO = 470 MHz, Low Power Mode Clock PLL, Processor Clock Divisor = 4, CMOS SSI

ADRV9002 Mode Conditions

Supply (mA)

Total Average

Power (W)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

1 × Receiver Low Power ADC, Low IF, 12.5 kHz Receiver Bandwidth,

24 kSPS Data Rate, Receiver QEC Enabled, QEC Engine Active, and

Transmitter Powered Down

Not used 92 171 26 3 0.367

1 × Transmitter RF Attenuation = 0 dB, Full-Scale Continuous Wave 12.5

kHz Transmitter Bandwidth, 96 kSPS Data Rate, Direct Modulation (DM)

Mode, Transmitter QEC Disabled, QEC Engine Inactive, and Receiver

Powered Down

Not used 62 257 100 3 0.582

1 × Transmitter RF Attenuation = 6 dB, Full-Scale Continuous Wave

12.5 kHz Transmitter Bandwidth, 96 kSPS Data Rate, DM Mode,

Transmitter QEC Disabled, QEC Engine Inactive, and Receiver Powered

Down

Not used 62 257 58 3 0.506

Table 9. LTE40 Two Transmitters and Two Receivers (2T2R), LO = 2.5 GHz, High Performance Clock PLL, LVDS SSI

ADRV9002 Mode Conditions

Supply (mA)

Total

Average

Power (W)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

2 × Receiver Low Power ADC Low Rate, 40 MHz Receiver Bandwidth,

61.44 MSPS Data Rate, Receiver QEC Enabled, QEC Engine Active, and

Transmitter in Primed State

Not used 446 546 64 53 1.366

2 × Transmitter RF Attenuation = 0 dB, Full-Scale Continuous Wave 40 MHz

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Disabled,

QEC Engine Inactive, and Receiver in Primed State

Not used 225 701 276 52 1.727

2 × Transmitter RF Attenuation = 10 dB, Full-Scale Continuous Wave 40 MHz

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Disabled,

QEC Engine Inactive, and Receiver in Primed State

Not used 225 701 120 52 1.446

2 × Transmitter RF Attenuation = 0 dB, Full-Scale Continuous Wave 40 MHz

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Disabled,

QEC Engine Active, Receiver in Primed State, Transmitter QEC Tracking

Always On, Observation Receiver Continuously On, and Transmitter Tracking

Duty Cycled (Practical Scenario)

Not used 397 1136 296 52 2.500

2 × Transmitter RF Attenuation = 10 dB, Full-Scale Continuous Wave 40 MHz

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Enabled,

QEC Engine Active, Receiver in Primed State, Transmitter QEC Tracking

Always On, Observation Receiver Continuously On, and Transmitter Tracking

Duty Cycled (Practical Scenario)

Not used 395 1126 144 52 2.212

Table 10. LTE40 One Transmitter and One Receiver (1T1R), LO = 2.5 GHz, High Performance Clock PLL, LVDS SSI

ADRV9002 Mode Conditions

Supply (mA)

Total

Average

Power (W)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

1 × Receiver Low Power ADC Low Rate, 40 MHz Receiver Bandwidth,

61.44 MSPS Data Rate, Receiver QEC Enabled, QEC Engine Active, and

Transmitter in Primed State

Not used 258 406 39 28 0.906

Data Sheet ADRV9002

SPECIFICATIONS

analog.com Rev. 0 | 17 of 92

Table 10. LTE40 One Transmitter and One Receiver (1T1R), LO = 2.5 GHz, High Performance Clock PLL, LVDS SSI

ADRV9002 Mode Conditions

Supply (mA)

Total

Average

Power (W)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

1 × Transmitter RF Attenuation = 0 dB, Full-Scale Continuous Wave 40 MHz

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Disabled,

QEC Engine Inactive, and Receiver in Primed State

Not used 140 486 143 28 1.080

1 × Transmitter RF Attenuation = 10 dB, Full-Scale Continuous Wave

40 MHz Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC

Disabled, QEC Engine Inactive, and Receiver in Primed State

Not used 141 486 66 28 0.942

1 × Transmitter RF Attenuation = 0 dB, Full-Scale Continuous Wave 40 MHz

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Enabled,

QEC Engine Active, Receiver in Primed State, Transmitter QEC Tracking

Always On, Observation Receiver Continuously On, and Transmitter Tracking

is Duty Cycled (Practical Scenario)

Not used 232 754 156 28 1.543

1 × Transmitter RF Attenuation = 10 dB, Full-Scale Continuous Wave

40 MHz Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC

Enabled, QEC Engine Active, Receiver in Primed State, Transmitter QEC

Tracking Always On, Observation Receiver Continuously On, and Transmitter

Tracking is Duty Cycled (Practical Scenario)

Not used 231 755 79 28 1.405

FDD Operation

Transmit channel enabled, 40 MHz transmitter bandwidth, 61.44 MSPS data rate, transmitter internal LO = 2.4 GHz, transmit QEC disabled,

QEC engine inactive, LVDS SSI. Receive channel enabled, 40 MHz receiver bandwidth, 61.44 MSPS data rate, receiver internal LO = 2.5 GHz,

high performance clock PLL, high performance receiver ADC low rate, receive QEC enabled, and QEC engine active. Using a low power ADC

decreases power consumption by approximately 110 mW per receiver channel. No auxiliary DACs or auxiliary ADCs are enabled.

Table 11. FDD Modes

ADRV9002 Mode Conditions

Supply (mA)

Total Average

Power (W)

VDDA_1P0 Analog

Supplies

VDD_1P0 Digital

Supply

VDDA_1P3 Analog

Supplies

VDDA_1P8 Analog

Supplies

VDD_1P8 Digital

Supply

1 × Receiver, 1 × Transmitter RF

Attenuation = 0 dB, Full-Scale Continuous

Wave

Not used 298 835 179 28 1.756

1 × Receiver, 1 × Transmitter

RF Attenuation = 10 dB, Full-Scale

Continuous Wave

Not used 298 835 103 28 1.619

2 × Receiver, 2 × Transmitter RF

Attenuation = 0 dB, Full-Scale Continuous

Wave

Not used 507 1234 344 53 2.826

2 × Receiver, 2 × Transmitter

RF Attenuation = 10 dB, Full-Scale

Continuous Wave

Not used 507 1234 190 53 2.549

TIMING SPECIFICATIONS

Table 12.

Parameter Min Typ Max Unit Test Conditions/Comments

SERIAL PERIPHERAL INTERFACE (SPI) TIMING

28 ns SPI_CLK period, 3-wire mode

22 ns SPI_CLK period, 4-wire mode

10 ns SPI_CLK pulse width

3 ns SPI_EN setup to first SPI_CLK rising edge

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