Intel架构指令集参考手册

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"Intel Architecture Software Developer’s Manual - Instruction Set Reference" Intel Architecture Software Developer’s Manual是一部包含Intel处理器技术详细信息的重要文档，主要分为三个卷：Basic Architecture、Instruction Set Reference和System Programming Guide。这部手册对于理解并有效地编写针对Intel架构的软件至关重要。 Volume 2，即“Instruction Set Reference”，专注于Intel处理器支持的指令集，这是编程人员和系统开发者进行低级别编程时的必备参考。此卷详细列出了Intel处理器的各种指令，包括它们的功能、操作数、执行时间和可能的异常等。这使得开发人员能够精确地控制处理器的操作，从而优化代码性能或实现特定功能。 Intel的指令集通常包括数据处理指令（如加法、减法和乘法）、逻辑操作指令（如AND、OR和NOT）、控制流指令（如跳转和循环）、内存访问指令、以及高级特性如浮点运算、向量运算和多线程支持等。这些指令在不同的处理器系列中可能会有所扩展或变化，例如在 Pentium Pro、Pentium 4、Core i3/i5/i7 和 Xeon 系列中都有不同的增强和新增指令。在评估设计需求时，开发人员需要同时参考所有三卷内容，确保全面了解Intel处理器的特性和限制。手册中还包含了关于处理器架构、寻址模式、内存管理、中断和异常处理、输入/输出等关键主题的详细信息。文档中的信息虽是1997年的，但Intel会定期更新其产品规格和描述。因此，开发者需要时刻关注最新的版本，以获取最准确的技术资料。值得注意的是，Intel明确声明，提供此文档并不授予任何知识产权许可，且不承担因产品销售或使用产生的任何责任，包括但不限于特定用途的适用性、商品性以及侵犯任何专利、版权或其他知识产权的责任。同时，Intel的产品不推荐用于医疗、救生或生命维持应用。总体而言，Intel Architecture Software Developer’s Manual是软件开发者和硬件工程师深入了解Intel处理器、优化代码性能和实现高效系统设计的宝贵资源。通过深入学习这部手册，读者可以掌握Intel处理器的精髓，从而在系统设计和编程实践中发挥出最大的效能。

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ABOUT THIS MANUAL

Chapter 8 — Processor Management and Initialization.

Defines the state of an Intel Archi-

tecture processor and its floating-point unit after reset initialization. This chapter also explains

how to set up an Intel Architecture processor for real-address mode operation and protected

mode operation, and how to switch between modes.

Chapter 9 — Memory Cache Control.

Describes the general concept of caching and the

caching mechanisms supported by the Intel Architecture. This chapter also describes the

memory type range registers (MTRRs) and how they can be used to map memory types of phys-

ical memory. MTRRs were introduced into the Intel Architecture with the Pentium

Pro

processor.

Chapter 10 — MMX™ Technology System Programming Model.

Describes those aspects

of the Intel MMX technology that must be handled and considered at the system programming

level, including task switching, exception handling, and compatibility with existing system envi-

ronments.

Chapter 11 — System Management Mode (SMM).

Describes the Intel Architecture’s system

management mode (SMM), which can be used to implement power management functions.

Chapter 12 — Machine Check Architecture.

Describes the machine check architecture,

which was introduced into the Intel Architecture with the Pentium processor.

Chapter 13 — Code Optimization.

Discusses general optimization techniques for program-

ming an Intel Architecture processor.

Chapter 14 — Debugging and Performance Monitoring.

Describes the debugging registers

and other debug mechanism provided in the Intel Architecture. This chapter also describes the

time-stamp counter and the performance monitoring counters.

Chapter 15 — 8086 Emulation.

Describes the real-address and virtual-8086 modes of the Intel

Architecture.

Chapter 16 — Mixing 16-Bit and 32-Bit Code.

Describes how to mix 16-bit and 32-bit code

modules within the same program or task.

Chapter 17 — Intel Architecture Compatibility.

Describes the programming differences

between the Intel 286, Intel386™, Intel486™, Pentium, and Pentium Pro processors. The differ-

ences among the 32-bit Intel Architecture processors (the Intel386, Intel486, Pentium, and

Pentium Pro processors) are described throughout the three volumes of the Intel Architecture

Software Developer’s Manual, as relevant to particular features of the architecture. This chapter

provides a collection of all the relevant compatibility information for all Intel Architecture

processors and also describes the basic differences with respect to the 16-bit Intel Architecture

processors (the Intel 8086 and Intel 286 processors).

Appendix A — Performance-Monitoring Counters.

Lists the events that can be counted with

the performance-monitoring counters and the codes used to select these events.

Appendix B — Model Specific Registers (MSRs).

Lists the MSRs available in the Pentium Pro

processor and their functions.

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ABOUT THIS MANUAL

NOTE

Avoid any software dependence upon the state of reserved bits in Intel Archi-

tecture registers. Depending upon the values of reserved register bits will

make software dependent upon the unspecified manner in which the

processor handles these bits. Depending upon reserved values risks incompat-

ibility with future processors.

1.4.3. Instruction Operands

When instructions are represented symbolically, a subset of the Intel Architecture assembly

language is used. In this subset, an instruction has the following format:

label: mnemonic argument1, argument2, argument3

where:

•

label

is an identifier which is followed by a colon.

•

mnemonic

is a reserved name for a class of instruction opcodes which have the same

function.

•

The operands argument1, argument2, and argument3 are optional. There may be from zero

to three operands, depending on the opcode. When present, they take the form of either

literals or identifiers for data items. Operand identifiers are either reserved names of

registers or are assumed to be assigned to data items declared in another part of the

program (which may not be shown in the example).

When two operands are present in an arithmetic or logical instruction, the right operand is the

source and the left operand is the destination.

For example:

LOADREG: MOV EAX, SUBTOTAL

In this example LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is

the destination operand, and SUBTOTAL is the source operand. Some assembly languages put

the source and destination in reverse order.

1.4.4. Hexadecimal and Binary Numbers

Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by

the character H (for example, F82EH). A hexadecimal digit is a character from the following set:

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F.

Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the

character B (for example, 1010B). The “B” designation is only used in situations where confu-

sion as to the type of number might arise.

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ABOUT THIS MANUAL

1.4.5. Segmented Addressing

The processor uses byte addressing. This means memory is organized and accessed as a

sequence of bytes. Whether one or more bytes are being accessed, a byte address is used to locate

the byte or bytes memory. The range of memory that can be addressed is called an

address

space

The processor also supports segmented addressing. This is a form of addressing where a

program may have many independent address spaces, called

segments

. For example, a program

can keep its code (instructions) and stack in separate segments. Code addresses would always

refer to the code space, and stack addresses would always refer to the stack space. The following

notation is used to specify a byte address within a segment:

Segment-register:Byte-address

For example, the following segment address identifies the byte at address FF79H in the segment

pointed by the DS register:

DS:FF79H

The following segment address identifies an instruction address in the code segment. The CS

CS:EIP

1.4.6. Exceptions

An exception is an event that typically occurs when an instruction causes an error. For example,

an attempt to divide by zero generates an exception. However, some exceptions, such as break-

points, occur under other conditions. Some types of exceptions may provide error codes. An

error code reports additional information about the error. An example of the notation used to

show an exception and error code is shown below.

#PF(fault code)

This example refers to a page-fault exception under conditions where an error code naming a

type of fault is reported. Under some conditions, exceptions which produce error codes may not

be able to report an accurate code. In this case, the error code is zero, as shown below for a

general-protection exception.

#GP(0)

See Chapter 5, Interrupt and Exception Handling, in the Intel Architecture Software Developer’s

Manual, Volume 3, for a list of exception mnemonics and their descriptions.

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