超低功耗非易失性内存设计：适用于被动RFID标签

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"这篇论文介绍了一种超低功耗非易失性内存，该内存是为无源RFID标签设计的，并在标准的0.18微米CMOS工艺中实现。新设计的记忆体能够在宽泛的电源电压和时钟频率范围内运行，具有新的低功耗操作模式。在电荷泵电路中，开关晶体管的阈值电压效应被几乎消除，从而提高了电路的泵送效率。实验结果表明，在1.2伏的电源电压和780千赫兹的时钟频率下，该192位内存的读取电流消耗为1.8微安（写入时为3.6微安），读取速率为1.3兆比特/秒（写入速率为0.8千字节/秒）。本文首先介绍了电子电路如硬件加密电路、射频识别（RFID）标签和模拟微调电路的快速发展对小型化嵌入式非易失性（NV）存储器需求的增长。传统的非易失性存储器在功耗和尺寸上存在限制，而这种新型超低功耗设计旨在解决这些问题。在技术细节方面，文章着重讨论了电荷泵电路的优化。电荷泵是一种用于提升电压的电路，尤其对于非易失性内存来说，其电压转换效率直接影响到电源消耗和整体性能。通过消除开关晶体管的阈值电压效应，电路能够更有效地工作，降低功耗，同时保持稳定的电压供应，这对于在低电压环境下工作的设备如无源RFID标签至关重要。 192位内存阵列的实现展示了这种设计的实际应用潜力。0.18微米的CMOS工艺允许在小面积上集成大量存储单元，这符合RFID标签对小巧轻便的要求。测量数据显示，即使在较高的数据传输速率下，该内存的电流消耗仍然极低，这意味着它能在电池寿命有限或完全依赖能量收集的系统中有效工作。此外，文中可能还涵盖了内存的访问速度、数据保留能力和耐久性等方面的研究，这些都是衡量非易失性内存性能的关键指标。通过优化这些特性，设计者可以确保内存既能快速读写，又能长时间保存数据，同时在各种操作条件下保持低功耗。这项工作为无源RFID标签和其他低功耗应用提供了一种创新的非易失性存储解决方案，其设计和实现都体现了对功耗、尺寸和性能的深度优化。"

An Ultra Low Power Non-volatile Memory

in Standard CMOS Process for Passive RFID Tags

Peng Feng, Yunlong Li, and Nanjian Wu*

Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China;

*nanjian@red.semi.ac.cn

Abstract-An ultra low power non-volatile memory is designed

in a standard CMOS process for passive RFID tags. The memory

can operate in a new low power operating scheme under a wide

supply voltage and clock frequency range. In the charge pump

circuit the threshold voltage effect of the switch transistor is

almost eliminated and the pumping efficiency of the circuit is

improved. An ultra low power 192-bit memory with a register

array is implemented in a 0.18μM standard CMOS process. The

measured results indicate that, for the supply voltage of 1.2 volts

and the clock frequency of 780KHz, the current consumption of

the memory is 1.8μA (3.6 μA) at the read (write) rate of

1.3Mb/s (0.8Kb/s).

I. INTRODUCTION

The rapid growth of electronic circuits such as hardware

encryption circuits, radio frequency identification (RFID) tags,

and analog trimming circuits is driving the need for small size

of embedded non-volatile (NV) memory. However, the typical

EEPROM or FLASH memory requires additional masks and

process steps so that a small size of embedded NV memory

results in the whole system chip must bear the additional cost.

So the ultra low power NV memory in standard CMOS

process receives much attention in recent years. A single poly

EEPROM cell was proposed, in which FN tunneling

phenomenon is employed to program/erase (P/E) the state of

the memory cell [1]. An embedded flash memory was

reported in [2]. Each bit cell includes a high voltage switch

and a SRAM data-latch. However, it suffers from large power

consumption. When a passive UHF RFID tag operates, its

supply voltage and clock frequency varies widely with the

configuration of the reader and tag, so the regulation circuit

and charge pump circuit are necessary to keep the supply

voltage stable and to generate the high voltage for the bit cell

programming. The area and power of these circuits usually

take up a large proportion of the chip [3]. Some attempts have

been made to improve the performance of the charge pump

circuit [4, 5]. However, the stage gain is still lower than the

supply voltage.

This paper presents an ultra low power NV memory with a

high efficiency charge pump circuit and a register array in a

0.18μm standard CMOS process for passive RFID tags. The

memory can be operated in a new operating scheme under a

wide supply voltage and clock frequency range. In the charge

pump circuit the influence of the threshold voltage of the

switch transistor is almost eliminated and the pumping

efficiency of the circuit is improved. In section II, the memory

circuits and operation principles are introduced. In section III,

the implementation and test results of the memory are given.

Finally, a conclusion is given in section IV.

II. M

EMORY CIRCUITS AND OPERATION PRINCIPLES

A. The Architecture of the Memory

The architecture of the memory is shown in Fig.1. It

consists of a NV cell array, a bit line controller, a column

decoder, a sense amplifier column, a charge pump, a register

array and the control logic module. The control logic module

manages the operation of the blocks. The bit line controller

controls the write operation of the NV memory. The column

decoder selects the active column. The sense amplifiers detect

the outputs of the active-column cells in read operation. The

charge pump generates a high voltage and a medium voltage

in write operation. The size of the NV memory is equal to that

of the register array. Each N-bit word in the NV cell array

corresponds to N-bit word in the register array. The data in the

NV array are first loaded into the register array for the

subsequently read operation which is both faster and

consumes much less power.

B. The Bit Cell and Operation Principles

Fig. 2 shows the schematics of the bit differential cell and

the sense amplifier. The bit cell consists of coupling

capacitors C

and C

and FN tunneling junctions M

, M

. C

, M

and M

, M

and M

) are interconnected

through common floating poly F (F_n). FN tunneling

phenomenon with small current density is used to perform

ultra low power P/E operations. The electrons can tunnel

through M

and M

to inject into the floating gates F and F_n

and through M

and M

to depart from the floating gates. In

Read mode, M

and M

also act as read transistors. The

capacitances of C

and C

are much larger than that of

tunneling junctions, so the bias voltages on C

and C

can

control the voltages of the floating gates. A large electric field

across the junctions can be established by biasing the nodes

Fig.1. The architecture of the memory

713

IEEE 2009 Custom Intergrated Circuits Conference (CICC)

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