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S3C6400X RISC Microprocessor User's Manual
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"S3C6400X用户手册,RISC微处理器,2008年2月28日,版本1.00"
三星的S3C6400是一款基于RISC架构的微处理器,其数据表(datasheet)提供了这款处理器的详细技术规格和使用指南。这份文档,"USER'S MANUAL S3C6400X RISCMicroprocessor",是针对开发者和工程师的专业参考资料,旨在帮助他们理解和应用S3C6400芯片。
S3C6400的发布日期标注为2008年2月28日,版本1.00,这通常意味着这是该处理器的初步技术资料,可能随着产品的更新和发展会有进一步的修订。然而,三星在文档中明确指出,他们对于可能出现的错误或遗漏不承担责任,并且保留随时对产品或产品规格进行改进而不事先通知的权利。这意味着购买者和开发者需要定期检查更新以获取最新的技术信息。
文档中的“Important Notice”部分强调,购买半导体设备(如S3C6400)并不自动获得三星或任何其他方的专利使用权。这表明在使用该芯片设计系统时,用户需要确保自己拥有所有必要的知识产权许可。
三星不提供任何形式的保修、保证或声明,关于其产品是否适用于特定用途,也不承担因产品应用或使用导致的任何责任。这种免责声明是典型的工业标准,旨在保护制造商免于因第三方的不当使用而产生的法律问题。
S3C6400作为一款RISC微处理器,可能包含高性能的CPU核心、内存接口、外设控制器等多个组件,适用于嵌入式系统设计,如移动设备、消费电子产品、工业控制等。在实际应用中,开发者需要参考此数据表来了解其寄存器配置、指令集、功耗特性、中断系统、时钟管理以及与其他硬件组件的交互方式等关键信息。
为了充分利用S3C6400,开发者需要熟悉RISC架构的基本原理,理解处理器的性能指标,如时钟速度、内存带宽、I/O能力等,并根据文档提供的信息进行系统级设计和软件开发。此外,由于三星可能会对产品进行改进,开发者必须密切关注三星的更新信息,以确保他们的设计与最新产品兼容。
xvi S3C6400X_USER’S MANUAL_REV 1.00
Table of Contents (Continued)
Chapter 14 LCD Controller
14.6.40 WIN4 Color key 1 Register .........................................................................................................14-64
14.6.41 Dithering Control 1Register ........................................................................................................14-65
14.6.42 WIN0 Color MAP .........................................................................................................................14-65
14.6.43 WIN1 Color MAP .........................................................................................................................14-66
14.6.44 WIN2 Color MAP .........................................................................................................................14-66
14.6.45 WIN3 Color MAP .........................................................................................................................14-66
14.6.46 WIN4 Color MAP .........................................................................................................................14-67
14.6.47 Window Palette control Register .................................................................................................14-67
14.6.48 I80 / RGB Trigger Control Register .............................................................................................14-68
14.6.49 LCD I80 Interface Control 0 ........................................................................................................14-68
14.6.50 LCD I80 Interface Control 1 ........................................................................................................14-69
14.6.51 LCD I80 Interface Command Control 0 .......................................................................................14-69
14.6.52 LCD I80 Interface Command Control 1 ......................................................................................14-71
14.6.53 I80 System Interface Manual Command Control 0 .....................................................................14-71
14.6.54 I80 System Interface Manual Command Control 1 .....................................................................14-72
14.6.55 I80 System Interface Manual Command Control 2 .....................................................................14-72
14.6.56 LCD I80 Interface Command ......................................................................................................14-73
14.6.57 Window 2's Palette Data .............................................................................................................14-73
14.6.58 Window 3's Palette Data .............................................................................................................14-74
14.6.59 Window 4's Palette Data .............................................................................................................14-74
14.6.60 WIN0 Palette Ram Access Address (not SFR) ..........................................................................14-74
14.6.61 WIN1 Palette Ram Access Address (not SFR) ..........................................................................14-75
Chapter 15 Post processor
15.1 Overview................................................................................................................................................15-1
15.2 Features ................................................................................................................................................15-2
15.3 A Source and Destination Image Data Format .....................................................................................15-3
15.3.1 DMA Mode Operation ....................................................................................................................15-4
15.3.2 FIFO Mode Operation....................................................................................................................15-7
15.4 Image Size and Scale Ratio..................................................................................................................15-7
15.5 DMA operation of Source and Destination Image.................................................................................15-9
15.5.1 Start address..................................................................................................................................15-10
15.5.2 End address...................................................................................................................................15-10
15.6 Frame Management of POST Processor..............................................................................................15-12
15.6.1 Per Frame Management Mode......................................................................................................15-12
15.6.2 Free Run Mode ..............................................................................................................................15-12
15.7 Register File Lists..................................................................................................................................15-13
15.7.1 MODE Control Register .................................................................................................................15-15
15.7.2 Pre-Scale Ratio Register ...............................................................................................................15-17
15.7.3 Pre-Scale Image Size Register......................................................................................................15-17
15.7.4 Source Image Size Register ..........................................................................................................15-18
15.7.5 Horizontal Main Scale Ratio Register ............................................................................................15-18
15.7.6 Vertical Main Scale Ratio Register ................................................................................................15-18
15.7.7 Destination Image Size Register ...................................................................................................15-19
15.7.8 Pre-Scale Shift Factor Register .....................................................................................................15-19
S3C6400X_USER’S MANUAL_REV 1.00 xvii
Table of Contents (Continued)
Chapter 15 Post processor
15.7.9 DMA Start Address Register .........................................................................................................15-20
15.7.10 DMA End Address Register.........................................................................................................15-21
15.7.11 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register.............................................15-22
15.7.12 Next Frame DMA Start Address Register ...................................................................................15-23
15.7.13 Next Frame DMA End Address Register.....................................................................................15-24
15.7.14 DMA Start address Register for Output Cb and Cr .....................................................................15-24
15.7.15 DMA End Address Register for Output Cb and Cr......................................................................15-25
15.7.16 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register for Output Cb and Cr ..........15-25
15.7.17 15.26 Next Frame DMA Start Address Register for Output Cb and Cr.......................................15-25
15.7.18 Next Frame DMA End Address Register for Output Cb and Cr..................................................15-26
15.7.19 POSTENVID Register to Enable Video Processing.................................................................... 15-26
15.7.20 MODE Control Register 2............................................................................................................15-27
Chapter 16 Tv scaler
16.1 Overview ...............................................................................................................................................16-1
16.2 Features................................................................................................................................................16-2
16.3 A Source and Destination Image Data Format.....................................................................................16-3
16.3.1 DMA Mode Operation....................................................................................................................16-4
16.3.2 FIFO Mode Operation....................................................................................................................16-7
16.4 Image Size and Scale Ratio..................................................................................................................16-7
16.5 DMA operation of Source and Destination Image ................................................................................16-9
16.5.1 Start address .................................................................................................................................16-10
16.5.2 End address...................................................................................................................................16-10
16.6 Frame Management of TV Scaler.........................................................................................................16-12
16.6.1 Per Frame Management Mode......................................................................................................16-12
16.6.2 Free Run Mode..............................................................................................................................16-12
16.7 Register File Lists .................................................................................................................................16-13
16.7.1 MODE Control Register.................................................................................................................16-15
16.7.2 Pre-Scale Ratio Register ...............................................................................................................16-17
16.7.3 Pre-Scale Image Size Register .....................................................................................................16-17
16.7.4 Source Image Size Register..........................................................................................................16-18
16.7.5 Horizontal Main Scale Ratio Register............................................................................................16-18
16.7.6 Vertical Main Scale Ratio Register................................................................................................16-18
16.7.7 Destination Image Size Register ...................................................................................................16-19
16.7.8 Pre-Scale Shift Factor Register.....................................................................................................16-19
16.7.9 DMA Start Address Register .........................................................................................................16-20
16.7.10 DMA End Address Register.........................................................................................................16-20
16.7.11 Current Frame (Buffer0) and Next Frame (Buffer1) Offset Register...........................................16-21
16.7.12 Next Frame DMA Start Address Register ...................................................................................16-21
16.7.13 Next Frame DMA End Address Register.....................................................................................16-22
16.7.14 DMA Start Address Register for Output Cb and Cr.....................................................................16-22
16.7.15 DMA End Address Register for Output Cb and Cr......................................................................16-23
16.7.16 Current Frame (Buffer0) and Next Frame (Buffer1) Offset Register for Output Cb and Cr ........16-23
16.7.17 Next Frame DMA Start Address Register for Output Cb and Cr.................................................16-23
16.7.18 Next Frame DMA End Address Register for Output Cb and Cr..................................................16-24
16.7.19 POSTENVID Register for Enable Video Processing...................................................................16-24
16.7.20 MODE Control Register 2............................................................................................................16-25
xviii S3C6400X_USER’S MANUAL_REV 1.00
Table of Contents (Continued)
Chapter 17 TV Encoder
17.1 Overview................................................................................................................................................17-1
17.2 Feature ..................................................................................................................................................17-1
17.3 Block diagram........................................................................................................................................17-2
17.4 Functional descriptions..........................................................................................................................17-3
17.4.1 Composition of analog composite signal ......................................................................................17-4
17.4.2 Common Ntsc System ..................................................................................................................17-5
17.4.3 Common Pal system .....................................................................................................................17-6
17.4.4 Composition of screen ...................................................................................................................17-7
17.4.5 Requested horizontal timing .........................................................................................................17-8
17.4.6 Requested vertical timing ..............................................................................................................17-9
17.4.7 Explaination of image enhancer termninology ..............................................................................17-10
17.4.8 Macrovision (Anti Taping) .............................................................................................................17-11
17.6 DAC board configure guide...................................................................................................................17-12
17.7 TV encoder register summary ..............................................................................................................17-13
17.8 Individual register descriptions..............................................................................................................17-14
17.8.1 TVENCREG1 ................................................................................................................................17-14
17.8.2 TVENCREG2 ................................................................................................................................17-15
17.8.3 TVENCREG3 ................................................................................................................................17-15
17.8.4 TVENCREG4 ................................................................................................................................17-15
17.8.5 TVENCREG5 ................................................................................................................................17-16
17.8.6 TVENCREG6 ................................................................................................................................17-16
17.8.7 TVENCREG7 ................................................................................................................................17-16
17.8.8 TVENCREG8 ................................................................................................................................17-17
17.8.9 TVENCREG9 ................................................................................................................................17-17
17.8.10 TVENCREG10 ............................................................................................................................17-18
17.8.11 TVENCREG11 ............................................................................................................................17-18
17.8.12 TVENCREG12 ............................................................................................................................17-18
17.8.13 TVENCREG14 ............................................................................................................................17-19
17.8.14 TVENCREG15 ............................................................................................................................17-19
17.8.15 TVENCREG18 ............................................................................................................................17-21
17.8.16 TVENCREG19 ............................................................................................................................17-21
17.8.17 TVENCREG20 ............................................................................................................................17-22
17.8.18 TVENCREG21 ............................................................................................................................17-23
17.8.19 TVENCREG23 ............................................................................................................................17-23
17.8.20 TVENCREG25 ............................................................................................................................17-24
17.8.21 TVENCREG26 .............................................................................................................................17-25
17.8.22 TVENCREG27 ............................................................................................................................17-25
17.8.23 TVENCREG28 ............................................................................................................................17-26
17.8.24 TVENCREG29 ............................................................................................................................17-26
17.8.25 TVENCREG30 ............................................................................................................................17-26
17.8.26 TVENCREG31 ............................................................................................................................17-27
17.8.27 TVENCREG32 ............................................................................................................................17-27
17.8.28 TVENCREG33 ............................................................................................................................17-27
S3C6400X_USER’S MANUAL_REV 1.00 xix
Table of Contents (Continued)
Chapter 18 GRPAHIC2D
18.1 Overview ...............................................................................................................................................18-1
18.2 Features................................................................................................................................................18-2
18.3 Color Format .........................................................................................................................................18-3
18.4 Rendering Pipeline................................................................................................................................18-3
18.4.1 Primitive Drawing ..........................................................................................................................18-3
18.4.2 Bit Block Transfer .........................................................................................................................18-4
18.4.3 Color Expansion (Font Drawing) ..................................................................................................18-5
18.4.4 Raster Operation ..........................................................................................................................18-6
18.4.5 Alpha Blending...............................................................................................................................18-7
18.4.6 Rotation ......................................................................................................................................... 18-8
18.4.7 Clipping .........................................................................................................................................18-9
18.5 Register Descriptions............................................................................................................................18-10
18.5.1 Memory Map .................................................................................................................................18-10
18.6 Individual Register Description .............................................................................................................18-12
18.6.1 General Interrupt Enable Register (INTEN_REG) .......................................................................18-12
18.6.2 General FIFO Interrupt Control Register (FIFO_INTC_REG) ......................................................18-12
18.6.3 General Interrupt Control Pending Register (INTC_PEND_REG) ...............................................18-13
18.6.4 General FIFO Status REGISTER (FIFO_STAT_REG) ................................................................18-13
18.6.5 General Frame Buffer Base Address Register (FB_BA_REG) ....................................................18-14
18.6.6 Command Line Drawing Register (CMD0_REG) .........................................................................18-14
18.6.7 Command BitBLT Register (CMD1_REG) ...................................................................................18-14
18.6.8 Command Host to Screen Start BitBLT Register (CMD2_REG) ..................................................18-15
18.6.9 Command Host to Screen Continue BitBLT Register (CMD3_REG) ...........................................18-15
18.6.10 Command Host to Screen Start Color Expansion Register (CMD4_REG) ................................18-15
18.6.11 Command Host to Screen Continue Color Expansion Register (CMD5_REG) .........................18-15
18.6.12 Command Memory to Screen Color Expansion Register (CMD7_REG) ...................................18-16
18.6.13 Common Resource Color Mode (COLOR_MODE_REG) ..........................................................18-16
18.6.14 Common Resource Horizontal Resolution (HORI_RES_REG) .................................................18-16
18.6.15 Common Resource Screen Clipping Window (SC_WIN_REG) .................................................18-17
18.6.16 Common Resource Screen Clipping Max_X Window (SC_WIN_X_REG) ...............................18-17
18.6.17 Common Resource Screen Clipping Max_Y Window (SC_WIN_Y_REG) ................................18-17
18.6.18 Common Resource Clipping Window LeftTop (CW_LT_REG) ..................................................18-18
18.6.19 Common Resource Left X Clipping Window (CW_LT_X_REG) ................................................18-18
18.6.20 Common Resource Top Y Clipping Window (CW_LT_Y_REG) ................................................18-18
18.6.21 Common Resource RightBottom Clipping Window (CW_RB_REG) .........................................18-19
18.6.22 Common Resource Right X Clipping Window (CW_RB_X_REG) .............................................18-19
18.6.23 Common Resource Bottom Y Clipping Window (CW_RB_Y_REG) ..........................................18-19
18.6.24 Common Resource Coordinate_0 Register (COORD0_REG) .................................................. 18-20
18.6.25 Common Resource Coordinate_0 X Register (COORD0_X_REG) ...........................................18-20
18.6.26 Common Resource Coordinate_0 Y Register (COORD0_Y_REG) ...........................................18-20
18.6.27 Common Resource Coordinate_1 Register (COORD1_ REG) .................................................18-21
18.6.28 Common Resource Coordinate_1 X Register (COORD1_X_REG) ...........................................18-21
18.6.29 Common Resource Coordinate_1 Y Register (COORD1_Y_REG) ...........................................18-21
18.6.30 Common Resource Coordinate_2 Register (COORD2_ REG) .................................................18-22
18.6.31 Common Resource Coordinate_2 X Register (COORD2_X_REG) ...........................................18-22
18.6.32 Common Resource Coordinate_2 Y Register (COORD2_Y_REG) ...........................................18-22
18.6.33 Common Resource Coordinate_3 Register (COORD3_ REG) .................................................18-23
18.6.34 Common Resource Coordinate_3 X Register (COORD3_X_REG) ...........................................18-23
18.6.35 Common Resource Coordinate_3 Y Register (COORD3_Y_REG) ...........................................18-23
xx S3C6400X_USER’S MANUAL_REV 1.00
Table of Contents (Continued)
Chapter 18 GRPAHIC2D
18.3.36 Common Resource Rotation Origin Coordinate (ROT_OC_REG) .............................................18-24
18.6.37 Common Resource Rotation Origin Coordinate X (ROT_OC_X_REG) .....................................18-24
18.6.38 Common Resource Rotation Origin Coordinate Y (ROT_OC_Y_REG) .....................................18-24
18.6.39 Common Resource Rotation Register (ROTATE_REG) ............................................................18-25
18.6.40 Common Resource Read Size (READSIZE) ..............................................................................18-25
18.6.41 Common Resource X Increment Register (X_INCR_REG) .......................................................18-26
18.6.42 Common Resource Y Increment Register (Y_INCR_REG) .......................................................18-26
18.6.43 Common Resource Raster Operation Register (ROP_REG) .....................................................18-26
18.6.44 Common Resource Alpha Register (ALPHA_REG) ...................................................................18-27
18.6.45 Common Resource Foreground Color Register (FG_COLOR_REG) ........................................18-27
18.6.46 Common Resource Background Color Register (BG_COLOR_REG) .......................................18-27
18.6.47 Common Resource BlueScreen Color Register (BS_COLOR_REG) ........................................18-27
18.6.48 Pattern Memory (PATTERN_REG) ............................................................................................18-28
18.6.49 Common Resource Pattern Offset Register (PATOFF_REG) ...................................................18-28
18.6.50 Common Resource Pattern Offset X Register (PATOFF_X_REG) ............................................18-28
18.6.51 Common Resource Pattern Offset Y Register (PATOFF_Y_REG) ............................................18-28
Chapter 19 Rotator
19.1 Overview................................................................................................................................................19-1
19.2 Feature ..................................................................................................................................................19-1
19.3 Block Diagram .......................................................................................................................................19-1
19.4 Image Example......................................................................................................................................19-2
19.5 Register Description..............................................................................................................................19-3
19.5.1 Memory Map .................................................................................................................................19-3
19.5.2 Rotator Control Register ...............................................................................................................19-3
19.5.3 Rotator Source Image Address Register 0 (RGB or Y component) .............................................19-4
19.5.4 Rotator Source Image Address Register 1 (Cb Component) .......................................................19-4
19.5.5 Rotator Source Image Address Register 2 (Cr Component) ........................................................19-4
19.5.6 Rotator Source Image Size Register ............................................................................................19-4
19.5.7 Rotator Destination Image Address Register 0 (RGB or Y Component) ......................................19-5
19.5.8 Rotator Destination Image Address Register 1 (CB Component) ................................................19-5
19.5.9 Rotator Destination Image Address Register 2 (CR Component) ................................................19-5
19.5.10 Rotator Status Register ...............................................................................................................19-5
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