Inter-Integrated Circuit (I
2
C) Interface ........................................................................................ 338
Register 1: I
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 352
Register 2: I
2
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 353
Register 3: I
2
C Master Data (I2CMDR), offset 0x008 ......................................................................... 357
Register 4: I
2
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 358
Register 5: I
2
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 359
Register 6: I
2
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 360
Register 7: I
2
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 361
Register 8: I
2
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 362
Register 9: I
2
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 363
Register 10: I
2
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 365
Register 11: I
2
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 366
Register 12: I
2
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 368
Register 13: I
2
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 369
Register 14: I
2
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 370
Register 15: I
2
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 371
Register 16: I
2
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 372
Analog Comparator ..................................................................................................................... 373
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 377
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 378
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 379
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 380
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 381
Register 6: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 382
Pulse Width Modulator (PWM) .................................................................................................... 384
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 392
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 393
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 394
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 395
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 396
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 397
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 398
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 399
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 400
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 401
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 401
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 401
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 403
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 403
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 403
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 405
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 405
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 405
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 406
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 406
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 406
Register 22: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 407
June 04, 200816
Preliminary
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