STM32G031系列Arm Cortex-M0+微控制器数据手册

需积分: 38 189 浏览量更新于2024-07-09 收藏 1.82MB PDF 举报

"STM32G031x4x6x8 数据手册是关于STM32G031系列微控制器的详细技术文档，涵盖了该系列芯片的主要特性、功能和应用范围。STM32G031是基于Arm Cortex-M0+内核的32位微控制器，适用于广泛的嵌入式应用，具有高性能、低功耗的特点。" STM32G031x4/x6/x8微控制器的关键特点包括： 1. **核心性能**：采用高效的Arm Cortex-M0+处理器内核，工作频率最高可达64MHz，提供了强大的处理能力。 2. **温度范围**：能够在-40°C到85°C甚至125°C的宽温范围内正常工作，适应各种环境条件。 3. **内存配置**：内置最大64KB的闪存（Flash）和8KB的带硬件奇偶校验的SRAM，满足存储程序和数据的需求。 4. **CRC计算单元**：集成CRC计算单元，用于数据完整性检查。 5. **电源管理**：支持1.7V至3.6V的工作电压范围，具备POR/PDR（上电/掉电复位）、BOR（可编程 brownout 复位）、PVD（可编程电压检测器）等功能，以及多种低功耗模式如Sleep、Stop、Standby和Shutdown，优化了能源效率。 6. **VBAT供电**：提供VBAT引脚，用于在主电源关闭时为RTC（实时时钟）和备份寄存器供电。 7. **时钟系统**：配备4到48MHz的晶体振荡器、32kHz晶体振荡器、内部16MHz RC振荡器（精度±1%）以及内部32kHz RC振荡器（精度±5%），确保精确的时钟源。 8. **GPIO接口**：多达44个快速输入/输出，所有I/O都可以映射到外部中断向量，并且有多个5V兼容I/O，增强了外部设备连接性。 9. **DMA控制器**：5通道DMA控制器，拥有灵活的映射功能，可实现高效的数据传输。 10. **模拟功能**：集成12位ADC，转换速度快至0.4μs，最多可连接16个外部通道，通过硬件过采样可达到16位精度，支持模拟信号的精确测量。此外，STM32G031系列还包含其他丰富的外设接口，如定时器、串行通信接口（如USART）、通信接口等，适用于物联网、工业控制、消费电子等多种应用场景。其低功耗特性使其成为电池供电或对能耗敏感的项目中的理想选择。总体来说，STM32G031系列是一款高度集成、功能强大的微控制器，适合需要高效能和低功耗的嵌入式系统设计。

Functional overview STM32G031x4/x6/x8

16/117 DS12992 Rev 1

externally through VBAT pin. When this pin is not available on the package, VBAT

bonding pad is internally bonded to the VDD/VDDA pin.

• V

REF+

is the input reference voltage for the ADC, or the output of the internal voltage

reference buffer (when enabled). When V

DDA

< 2 V, V

REF+

must be equal to V

DDA

When V

DDA

≥ 2 V, V

REF+

must be between 2 V and V

DDA

. It can be grounded when the

ADC is not active.

The internal voltage reference buffer supports two output voltages, which is configured

with VRS bit of the VREFBUF_CSR register:

–V

REF+

around 2.048 V (requiring V

DDA

equal to or higher than 2.4 V)

–V

REF+

around 2.5 V (requiring V

DDA

equal to or higher than 2.8 V)

REF+

is delivered through VREF+ pin. On packages without VREF+ pin, V

REF+

internally connected with V

, and the internal voltage reference buffer must be kept

disabled (refer to datasheets for package pinout description).

• V

CORE

An embedded linear voltage regulator is used to supply the V

CORE

internal digital

power. V

CORE

is the power supply for digital peripherals, SRAM and Flash memory.

The Flash memory is also supplied with V

Figure 2. Power supply overview

3.7.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power

modes except Shutdown and ensuring proper operation upon power-on and power-down. It

maintains the device in reset when the supply voltage is below V

POR/PDR

threshold, without

the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It

MSv47940V1

DDA

domain

RTC domain

A/D converter

Standby circuitry

(Wakeup logic,

IWDG)

Voltage regulator

Core

SRAM

Digital

peripherals

Low-voltage

detector

LSE crystal 32.768 KHz osc

BKP registers

RCC BDCR register

RTC

Voltage reference buffer

I/O ring

CORE

domain

Temp. sensor

Reset block

PLL, HSI

Flash memory

DDIO1

VREF+

domain

CORE

VSS

VDD

VBAT

DDA

REF+

SSA

DS12992 Rev 1 17/117

STM32G031x4/x6/x8 Functional overview

can be enabled and configured through option bytes, by selecting one of four thresholds for

rising V

and other four for falling V

The device also features an embedded programmable voltage detector (PVD) that monitors

the V

power supply and compares it to V

PVD

threshold. It allows generating an interrupt

when V

level crosses the V

PVD

threshold, selectively while falling, while rising, or while

falling and rising. The interrupt service routine can then generate a warning message and/or

put the MCU into a safe state. The PVD is enabled by software.

3.7.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator

(LPR), supply most of digital circuitry in the device.

The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power

sleep and Stop modes.

In Standby and Shutdown modes, both regulators are powered down and their outputs set in

high-impedance state, such as to bring their current consumption close to zero. However,

SRAM data retention is possible in Standby mode, in which case the LPR remains active

and it only supplies the SRAM.

3.7.4 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the

user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

CORE

supplied by the low-power regulator to minimize the

regulator's operating current. The code can be executed from SRAM or from Flash,

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Low-

power run mode.

• Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while

retaining the SRAM and register contents. All clocks in the V

CORE

domain are stopped.

The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are

disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,

so as to get clock for processing the wakeup event. The main regulator remains active

in Stop 0 mode while it is turned off in Stop 1 mode.

• Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR

always active in this mode. The main regulator is switched off to power down V

CORE

domain. The low-power regulator is either switched off or kept active. In the latter case,

Functional overview STM32G031x4/x6/x8

18/117 DS12992 Rev 1

it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC

oscillator and the HSE crystal oscillator are also powered down. The RTC can remain

active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor

shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC

domain and standby circuitry. The SRAM contents can be retained through register

setting.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE

(CSS on LSE).

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal

regulator is switched off to power down the V

CORE

domain. The PLL, as well as the

HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The

RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible

in this mode. Therefore, switching to RTC domain is not supported.

SRAM and register contents are lost except for registers in the RTC domain.

The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper).

3.7.5 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce

power consumption. In addition, when the reset source is internal, the built-in pull-up

resistor on NRST pin is deactivated.

3.7.6 VBAT operation

The V

BAT

power domain, consuming very little energy, includes RTC, and LSE oscillator and

backup registers.

In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for

example, an external battery or an external supercapacitor. Two anti-tamper detection pins

are available.

The RTC domain can also be supplied from VDD/VDDA pin.

By means of a built-in switch, an internal voltage supervisor allows automatic switching of

RTC domain powering between V

and voltage from VBAT pin to ensure that the supply

voltage of the RTC domain (V

BAT

) remains within valid operating conditions. If both voltages

are valid, the RTC domain is supplied from VDD/VDDA pin.

An internal circuit for charging the battery on VBAT pin can be activated if the V

voltage is

within a valid range.

Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT

mode, as in that mode the V

is not within a valid range.

Functional overview STM32G031x4/x6/x8

20/117 DS12992 Rev 1

3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and

the peripherals. It also manages clock gating for low-power modes and ensures clock

robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

• System clock source: three different sources can deliver SYSCLK system clock:

– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It

can supply clock to system PLL. The HSE can also be configured in bypass mode

for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can

supply clock to system PLL.

– System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or

HSI16 clocks.

• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

capability modes. The LSE can also be configured in bypass mode for using an

external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to

clock an independent watchdog.

• Peripheral clock sources: several peripherals (I2S, USARTs, I2Cs, LPTIMs, ADC)

have their own clock independent of the system clock.

• Clock security system (CSS): in the event of HSE clock failure, the system clock is

automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE

clock failure can also be detected and generate an interrupt. The CCS feature can be

enabled by software.

• Clock output:

– MCO (microcontroller clock output) provides one of the internal clocks for

external use by the application

– LSCO (low speed clock output) provides LSI or LSE in all low-power modes

(except in VBAT operation).

Several prescalers allow the application to configure AHB and APB domain clock

frequencies, 64 MHz at maximum.

3.10 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of

the GPIO pins are shared with special digital or analog functions.

剩余116页未读，继续阅读

格利

粉丝: 0
资源: 10

STM32G031系列Arm Cortex-M0+微控制器数据手册

STM32F030x4x6x8xC微控制器中文手册全解

STM32F051x4/x6/x8微控制器数据手册：ARM Cortex-M0, 16-64KB Flash, 电源管理

STM32F051x8微控制器参考手册：内存与外设详解

STM32G030x6_x8_C6_F6_J6_K6_C8_K8中文数据手册.pdf

APM32F103x4x6x8xB数据手册V1.2.pdf

STM32F030x数据手册.pdf

STM32F030x4x6x8xC中文手册

STM32F051x4/STM32F051x6/STM32F051x8数据手册

stm32f030中文用户手册.pdf

STM32F030x4/STM32F030x6/STM32F030x8/STM32F030xC数据手册

最新资源