Altera FPGA FIFO Megafunctions用户指南

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“Altera FPGA Resource提供了FPGA FIFO应用笔记，主要介绍了单时钟FIFO (SCFIFO)和双时钟FIFO (DCFIFO)两种参数化宏功能，适用于同步或异步时钟域中的数据缓冲应用，符合先进先出的数据流原则。” 本文档是Altera公司关于FPGA中FIFO使用的用户指南，版本为UG-MFNALT_FIFO-6.0，发布于2009年9月。FPGA中的FIFO（First-In-First-Out，先进先出）宏功能主要用于数据缓冲，确保数据按照进入的顺序依次被处理。FPGA中的FIFO分为两类：单时钟FIFO (SCFIFO)和双时钟FIFO (DCFIFO)，其中DCFIFO还包含了支持输入和输出数据宽度不同的混合宽度版本。在文档中，“DCFIFO”一词通常指的是DCFIFO和DCFIFO_MIXED_WIDTHS宏功能，除非特别指出。这份用户指南涵盖了以下关键部分： 1. **配置方法**：这部分详细说明了如何配置SCFIFO和DCFIFO，包括设置参数和实现不同功能的方法。 2. **端口规格**：详细列出了FIFO宏功能的输入、输出端口要求，如数据宽度、读写使能信号等，以及它们如何与系统接口。 3. **参数规格**：提供了可配置的参数列表，包括深度、数据宽度、读写模式等，以及这些参数对性能和资源利用率的影响。 4. **功能时序要求**：阐述了FIFO在操作中必须满足的时序约束，这对于确保正确数据传输至关重要，特别是在跨越不同时钟域时。 5. **输出状态标志和延迟**：解释了FIFO提供的一系列状态标志，如空、满标志，以及数据读取和写入的延迟特性，帮助用户理解和管理FIFO的使用。 6. ** metastability保护**：讨论了在时钟域跨越中防止 metastability（不稳定的中间状态）的策略，这是高速数据传输中的一个常见问题，必须通过适当的同步电路来解决。此外，文档可能还包含了故障排查指南、实例分析和设计示例，帮助用户更好地理解和应用这些FIFO宏功能到实际的设计中。对于使用Altera FPGA进行数据处理和通信系统的开发者来说，这是一份非常有价值的参考资料。通过深入理解并灵活运用FIFO，可以优化系统的数据流管理，提高系统效率和可靠性。

Port Specifications Page 5

q (3) Output Yes Shows the data read from the read request operation.

For the SCFIFO megafunction and DCFIFO megafunction, the width of the

q port must be equal to the width of the data port. If you manually

instantiate the megafunctions, ensure that the port width is equal to the

LPM_WIDTH parameter.

For the DCFIFO_MIXED_WIDTHS megafunction, the width of the q port

can be different from the width of the data port. If you manually

instantiate the megafunction, ensure that the width of the q port is equal

to the LPM_WIDTH_R parameter. The megafunction supports a wide

write port with a narrow read port, and vice versa. However, the supported

width ratio is restricted by the type of RAM block used, and in general, are

in the power of 2. See “Different Input and Output Width” on page 18.

full (1)

wrfull (2)

rdfull (2)

Output No When asserted, the FIFO megafunction is considered full. Do not perform

write request operation when the FIFO megafunction is full.

In general, the rdfull signal is a delayed version of the wrfull signal.

However, for Stratix III device and onwards, the rdfull signal is a

combinational output instead of being the derived version of the wrfull

signal. Therefore, you should always refer to the wrfull port to ensure

whether or not a valid write request operation can be performed,

regardless of the target device.

empty (1)

wrempty (2)

rdrempty (2)

Output No When asserted, the FIFO is considered empty. Do not perform read

request operation when FIFO megafunction is empty.

In general, the wrempty signal is a delayed version of the rdempty

signal. However, for Stratix III device and onwards, the wrempty signal

is a combinational output instead of being the derived version of

rdempty signal. Therefore, you should always refer to the rdempty

port to ensure whether or not a valid read request operation can be

performed, regardless of the target device.

almost_full

(1) Output No Asserted when the usedw signal is greater than or equal to the

ALMOST_FULL_VALUE parameter. It is used as an early indication of

the full signal.

almost_empty (1) Output No Asserted when the usedw signal is less than the

ALMOST_EMPTY_VALUE parameter. It is used as an early indication of

the empty signal.

Table 1. Input and Output Ports Description (Part 3 of 4)

Port Type Required Description

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