QSFP-DD400G/800G硬件规范：高速光模块接口详解

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"高速光模块400G 800G QSFP-DD 硬件协议详细描述了QSFP-DD（Quad Small Form-Factor Pluggable Double Density）硬件规格，包括外形尺寸、金手指接口定义，适用于400Gbps至800Gbps的高速数据传输应用。该规范由QSFP-DD MSA（多源协议）制定，旨在为系统制造商、系统集成商和模块供应商提供统一的标准。" QSFP-DD（四倍小外形可插拔双密度）是一种高性能的光学模块接口，设计用于满足数据中心对高带宽的需求。400G QSFP-DD模块是400 Gigabit Ethernet和其它高速网络应用的理想选择，而800G QSFP-DD则进一步提升了数据传输速率，适应未来网络的扩展需求。在硬件协议中，QSFP-DD模块的外形尺寸和金手指接口是关键部分。QSFP-DD保持了与传统QSFP模块的外形兼容性，但提供更多的信号引脚，以实现更高的数据速率。金手指接口定义了模块与主板之间的电气连接，确保数据的稳定传输。此外，这些规格还涵盖了电气信号、电源供应、机械结构以及热管理要求，确保模块在各种环境条件下的可靠运行。模块的电气和光学连接器部分规定了如何实现高效的数据传输和信号完整性。这包括光信号的编码、解码方式，以及光纤接口类型，如多模或单模光纤，以适应不同距离和带宽的需求。热设计是高速光模块中不可忽视的部分，因为高功率消耗会导致温度上升，可能影响性能。QSFP-DD硬件规范中包含了关于散热和冷却解决方案的要求，以确保模块在高负荷工作时仍能保持稳定。此外，QSFP-DD MSA的联系方式和官方网站也被提及，用户可以访问网站获取最新版本的规范和其他相关资源。该协议的使用受限，通常需要遵循特定的条款和条件，以保护知识产权并促进行业的健康发展。高速光模块400G 800G QSFP-DD硬件协议详细规定了此类模块的设计、制造和互操作性标准，旨在推动高速网络技术的发展，并为行业内的标准化合作提供基础。

Published QSFP-DD/QSFP-DD800/QSFP112 HW Rev 6.01

For EMI protection the signals from the host connector should be shut off when the QSFP-DD/QSFP-DD800

modules are not present. Standard board layout practices such as connections to Vcc and GND with vias, use

of short and equal-length differential signal lines are recommended. The chassis ground (case common) of the

QSFP-DD/QSFP-DD800 modules should be isolated from the module’s circuit ground, GND, to provide the

equipment designer flexibility regarding connections between external electromagnetic interference shields and

circuit ground, GND, of the module.

Figure 2: Module pad assignment and layout

GND

TX1n

TX1p

GND

TX3n

TX3p

GND

LPMode/TxDis

Vcc1

VccTx

IntL/RxLOS

ModPrsL

GND

RX4p

RX4n

GND

RX2p

RX2n

GND

TX5n

TX5p

GND

TX7n

TX7p

GND

ePPS/Clock

Vcc2

VccTx1

Reserved

GND

RX8p

RX8n

GND

RX6p

RX6n

GND

(Module Side)

Module Card Edge (Host Side)

Top PCB viewed from top

GND

RX5n

RX5p

GND

RX7n

RX7p

GND

P/VS3

P/VS2

VccRx1

P/VS1

P/VS4

GND

TX8p

TX8n

GND

TX6p

TX6n

GND

(Module Side)

Module Card Edge (Host Side)

GND

RX1n

RX1p

GND

RX3n

RX3p

GND

SDA

SCL

VccRx

ResetL

ModSelL

GND

TX4p

TX4n

GND

TX2p

TX2n

GND

Additional

QSFP-DD/QSFP-DD800 Pads

Classic

QSFP+/QSFP28/QSFP112 Pads

Bottom PCB viewed from bottom

Plug Sequence 1B

Plug Sequence 1A

Published QSFP-DD/QSFP-DD800/QSFP112 HW Rev 6.01

Pad

Logic

Symbol

Description

Plug

Sequence

Notes

LVCMOS

/CML-I

P/VS4

Programmable/Module Vendor Specific 4

LVCMOS

/CML-I

P/VS1

Programmable/Module Vendor Specific 1

VccRx1

3.3V Power Supply

LVCMOS

/CML-O

P/VS2

Programmable/Module Vendor Specific 2

LVCMOS

/CML-O

P/VS3

Programmable/Module Vendor Specific 3

GND

Ground

CML-O

Rx7p

Receiver Non-Inverted Data Output

CML-O

Rx7n

Receiver Inverted Data Output

GND

Ground

CML-O

Rx5p

Receiver Non-Inverted Data Output

CML-O

Rx5n

Receiver Inverted Data Output

GND

Ground

GND

Ground

CML-O

Rx6n

Receiver Inverted Data Output

CML-O

Rx6p

Receiver Non-Inverted Data Output

GND

Ground

CML-O

Rx8n

Receiver Inverted Data Output

CML-O

Rx8p

Receiver Non-Inverted Data Output

GND

Ground

No Connect

Reserved

For future use

VccTx1

3.3V Power Supply

Vcc2

3.3V Power Supply

LVCMOS-I

ePPS/Clock

1PPS PTP clock or reference clock input

GND

Ground

CML-I

Tx7p

Transmitter Non-Inverted Data Input

CML-I

Tx7n

Transmitter Inverted Data Input

GND

Ground

CML-I

Tx5p

Transmitter Non-Inverted Data Input

CML-I

Tx5n

Transmitter Inverted Data Input

GND

Ground

Note 1: QSFP-DD uses common ground (GND) for all signals and supply (power). All are common within the QSFP-

DD module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to

the host board signal-common ground plane. Each connector Gnd contact is rated for a maximum current of 500 mA.

Note 2: VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 shall be applied concurrently. Supply requirements defined

for the host side of the Host Card Edge Connector are listed in Table 10. For power classes 4 and above the module

differential loading of input voltage pads must not result in exceeding contact current limits. Each connector Vcc

contact is rated for a maximum current of 1500 mA.

Note 3: Reserved and no Connect pads recommended to be terminated with 10 k to ground on the host. Pad 65 (No

Connect) shall be left unconnected within the module.

Note 4: Plug Sequence specifies the mating sequence of the host connector and module. The sequence is 1A, 2A, 3A,

1B, 2B, 3B. (see Figure 2 for pad locations) Contact sequence A will make, then break contact with additional QSFP-

DD pads. Sequence 1A and 1B will then occur simultaneously, followed by 2A and 2B, followed by 3A and 3B.

Note 5: Full definitions of the P/VSx signals currently under development. On new designs not used P/VSx signals are

recommended to be terminated on the host with 10 k

Note 6: ePPS/Clock if not used recommended to be terminated with 50  to ground on the host.

Published QSFP-DD/QSFP-DD800/QSFP112 HW Rev 6.01

4.2 Low Speed Electrical Hardware Signals

In addition to the TWI serial interface the module has the following low speed signals for control and status:

• ModSelL

• ResetL

• LPMode/TxDis

• ModPrsL

• IntL/RxLOSL

• P/VS1, P/VS2, P/VS3, and P/VS4.

• ePPS/Clock

4.2.1 ModSelL

The ModSelL is an input signal that shall be pulled to Vcc in the QSFP-DD/QSFP-DD800 modules (see Table

5). When held low by the host, the module responds to TWI serial communication commands. The ModSelL

allows the use of multiple QSFP-DD/QSFP-DD800 modules on a single TWI interface bus. When ModSelL is

“High”, the module shall not respond to or acknowledge any TWI interface communication from the host.

In order to avoid conflicts, the host system shall not attempt TWI interface communications within the ModSelL

de-assert time after any QSFP-DD/QSFP-DD800 modules are deselected. Similarly, the host must wait at least

for the period of the ModSelL assert time before communicating with the newly selected module. The assertion

and de-asserting periods of different modules may overlap as long as the above timing requirements are met.

4.2.2 ResetL

The ResetL signal shall be pulled to Vcc in the module (see Table 5). A low level on the ResetL signal for

longer than the minimum pulse length (t_Reset_init) (See Table 7) initiates a complete module reset, returning

all user module settings to their default state.

4.2.3 LPMode/TxDis

LPMode/TxDis is a dual-mode input signal from the host operating with active high logic. It shall be pulled

towards Vcc in the module. At power-up or after ResetL is deasserted LPMode/TxDis behaves as LPMode. If

supported, LPMode/TxDis can be configured as TxDis using the TWI interface except during the execution of a

reset. Timing requirements for LPMode/TxDis mode changes are found in, see Table 7. LPMode is used in

the control of the module power mode, see CMIS [5] Chapter 6.3.1.3.

When LPMode/TxDis is configured as LPMode, the module behaves as though TxDis=0. By using the

LPMode signal and a combination of the Power_override, Power_set and High_Power_Class_Enable software

control bits the host controls how much power a module can consume. When LPMode/TxDis is configured as

TxDis, the module behaves as though LPMode=0. In this mode LPMode/TxDis when set to 1 or 0 disables or

enables all optical transmitters within the times specified in Table 7.

Changing LPMode/TxDis mode from LPMode to TxDis when the LPMode/TxDis state is high disables all

optical transmitters. If the module was in low power mode, then the module transitions out of low power mode

at the same time. If the module is already in high power state (Power Override control bits) with transmitters

already enabled, the module shall disable all optical transmitters. Changing the LPMode/TxDis mode from

LPMode to TxDis when the LPMode/TxDis state is low, simply changes the behavior of the mode of

LPMode/TxDis. The behavior of the module depends on the Power Override control bits.

Note that the “soft” functions of TxDis, LPMode, IntL and RxLOSL allow the host to poll or set these values

over the TWI interface as an alternative to monitoring/setting signal values. Asserting either the “hardware” or

“soft bit” (or both) for TxDis or LPMode results in that function being asserted.

Published QSFP-DD/QSFP-DD800/QSFP112 HW Rev 6.01

Editor’s Note: registers to support optional TxDis will be added in future revisions of CMIS.

4.2.4 ModPrsL

ModPrsL shall be pulled up to Vcc Host on the host board and pulled low in the module (see Table 5). The

ModPrsL is asserted “Low” when the module is inserted. The ModPrsL is deasserted “High” when the module

is physically absent from the host connector due to the pull-up resistor on the host board.

4.2.5 IntL/RxLOSL

IntL/RxLOSL is a dual-mode active-low, open-collector output signal from the module. It shall be pulled up

towards Vcc on the host board (see Table 5). At power-up or after ResetL is released to high, IntL/RxLOSL is

configured as IntL. When the IntL signal is asserted Low it indicates a change in module state, a possible

module operational fault or a status critical to the host system. The host identifies the source of the interrupt

using the TWI serial interface. The IntL signal is deasserted “High” after all set interrupt flags are read. If dual

mode operation supported, IntL/RxLOSL can be optionally programmed as RxLOSL using the TWI interface

except during the execution of a reset. If the module has no interrupt flags asserted (IntL/RxLOSL is high),

there should be no change in IntL/RxLOSL states after the mode change.

If IntL/RxLOSL is configured as RxLOSL, a low indicates that there is a loss of received optical power on at

least one lane. “high” indicates that there is no loss of received optical power. Timing requirements for

IntL/RxLOSL including fast RxLOS mode are found in Table 7. The actual condition of loss of optical receive

power is specified by other governing documents, as the alarm threshold level is application specific. The

module shall pull RxLOSL to low if any lane in a multiple lane module or cable has a LOS condition and shall

release RxLOSL to high only if no lane has a LOS condition.

Editor’s note: registers to support optional RxLOSL will be added in future revisions of CMIS.

4.2.6 Programmable/Vendor Specific (Optional)

QSFP-DD MSA provides 2 input programmable/vendor specific pads (P/VS1, P/VS4) and 2 output

programable/vendor specific pads (P/VS2, P/VS3). Programmable use case also includes vendor proprietary

applications. P/VSx I/O are disabled by default.

Editor’s Note - Logic definitions and programmable use cases for P/VSx input/output pads expect to be defined

by QSFP-DD HW MSA and CMIS.

4.2.7 ePPS/Clock PTP Reference Clock (Optional)

Host ePPS/Clock The ePPS/Clock input is a programable timing and clock input, that can support

unmodulated 1PPS (1 pulse per second), modulated (1PPS), and reference clock. The ePPS/clock is a

LVCMOS compatible signal with series termination (TBD) on the host board and a parallel termination of at

least 4.7 k in the module. To improve signal integrity for faster clocks (i.e., 156.25 MHz) the parallel

termination can be reduced to as low as 470  and optionally AC coupled.

For high-performance Precision Time Protocol (PTP) applications, the ePPS (Enhanced Pulse Per Second)

reference either with 1PPS modulated or unmodulated may be provided from the host to the module for time

synchronization, see Table 2 for advertise capability. This can be used for either offline delay characterization

or real-time delay compensation within the module. The ePPS is used to synchronize tightly the Host Time-of-

Day counter to the module internal Time-of-Day Counter.

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