5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RC300M_X2
RC300M_X1
CLK_AGP_66M CLK_MEM_66M
CLK_AGP_66M
+1.8VS_LPVDD
+1.8VS_LVDDR
CRMA_R
COMPS_R
LUMA_R
HSYNC_R
GREEN_R
RED_R
BLUE_R
VSYNC_R
NB_RSET
CLK_NB_BCLK#
CLK_NB_BCLK
RC300M_X2
3VDDCCL
DDCDATA_R
DDCCLK_R
CRMA_R
3VDDCDA
DDCDATA_R
DDCCLK_R
CLK_MEM_66M
GREEN_RCRT_G
VSYNC_R
CRT_B BLUE_R
CRT_HSYNC
CRT_R
HSYNC_R
RED_R
CRT_VSYNC
RC300M_X1
TV_CRMA
LUMA_R TV_LUMA
TV_COMPSCOMPS_R
27M_TV_R27M_TV
CLK_AGP_66M<23>
TXACLK-_NB <24>
TXA0+_NB <24>
TXB0+_NB <24>
TXB2+_NB <24>
TXBCLK-_NB <24>
TXB2-_NB <24>
TXA1-_NB <24>
TXBCLK+_NB <24>
TXA0-_NB <24>
TXB1+_NB <24>
TXB1-_NB <24>
TXA2-_NB <24>
TXACLK+_NB <24>
TXA2+_NB <24>
CPUCLK_STP# <5,25,28,53>
CLK_NB_BCLK#<23>
CLK_NB_BCLK<23>
3VDDCCL <16,24>
TV_LUMA <16,24,43>
TV_COMPS <16,24>
TV_CRMA <16,24,43>
3VDDCDA <16,24>
CLK_MEM_66M<23>
CRT_HSYNC<16,24>
CRT_VSYNC<16,24>
CRT_B<16,24,43>
CRT_R<16,24,43>
CRT_G<16,24,43>
REFCLK1_NB<23>
TXB0-_NB <24>
TXA1+_NB <24>
NB_RST# <8,16,25,38>
CPUSTOP# <23>
+1.8VS
+1.8VS
+3VS
+3VS
+2.5VS
+1.8VS
+1.8VS
+1.8VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet
of
401257
0E
SCHEMATIC, M/B LA-1861
11 61,
星期三 七月
30, 2003
Compal Electronics, Inc.
Note: PLACE CLOSE TO (NB CHIP)
Note: PLACE CLOSE TO (NB CHIP)
BOM update 6/16
Layout & BOM update 7/10
R399
KC FBM-L11-201209-221LMAT_0805
1 2
R84 0_0402_5%
R101
10_0402_5%
12
R363 M9@0_0402_5%
1 2
G
D
S
Q47
@2N7002_SOT23
2
1 3
L61
KC FBM-L11-201209-221LMAT_0805
1 2
C95
@18P_0402_50V8K
C127
15P_0402_50V8D
L62
KC FBM-L11-201209-221LMAT_0805
1 2
R395
10_0402_5%
12
R365 M9@0_0402_5%
1 2
C73
0.1U_0402_16V4Z
1
2
C119
@18P_0402_50V8K
C464
15P_0402_50V8D
C481
0.1U_0402_16V4Z
1
2
C75
@0.1U_0402_16V4Z
1
2
Y2
@14.31818MHZ_20P_6X1430004201
12
C86
0.1U_0402_16V4Z
1
2
R368 M9@0_0402_5%
1 2
C103 0.1U_0402_16V4Z
1
2
C482
0.1U_0402_16V4Z
1
2
R70
KC FBM-L11-201209-221LMAT_0805
1 2
R72 M9@0_0402_5%
1 2
C484
0.1U_0402_16V4Z
1
2
X2
@27MHZ_15P
OUT
3
GND
2
VDD
4
OE
1
R91
@1M_0402_1%
R88
68_0603_1%
R401 @0_0402_5%
R361 M9@0_0402_5%
1 2
R73 @22_0402_5%
R68 M9@0_0402_5%
1 2
L60
KC FBM-L11-201209-221LMAT_0805
1 2
R63 M9@0_0402_5%
1 2
R402
4.7K_0402_5%
C483
0.1U_0402_16V4Z
1
2
C102
0.1U_0402_16V4Z
1
2
C74
0.1U_0402_16V4Z
1
2
R75
715_0402_1%
1 2
R62 M9@0_0402_5%
1 2
C468
10U_0805_10V4Z
C104
0.1U_0402_16V4Z
1
2
PAR T 4 OF 6
CRT
CLK. GEN.
SVID
LVDS
U11D
216RC300M_BGA_718
TXOUT_U0N
D12
TXOUT_U0P
E12
TXOUT_U1N
F11
TXOUT_U1P
F12
TXOUT_U2N
D13
TXOUT_U2P
D14
TXCLK_UN
E13
TXCLK_UP
F13
TXOUT_L0N
E10
TXOUT_L0P
D10
TXOUT_L1N
B9
TXOUT_L1P
C9
TXOUT_L2N
D11
TXOUT_L2P
E11
TXCLK_LN
B10
TXCLK_LP
C10
LVDDR_18
B12
LPVSS
A11
LVDDR_18
C12
LPVDD_18
A12
LVSSR
B11
LVSSR
C11
C_R
E15
Y_G
C15
COMP_B
D15
DACSCL
D6
DACSDA
C6
CPUSTOP#
D5
RED
F14
GREEN
F15
BLUE
E14
DACHSYNC
C8
DACVSYNC
D9
RSET
C14
VDDR3
H9
AVDDQ
A15
AVSSN
B13
AVDD_25
A14
AVDDDI_18
B14
AVSSDI
C13
AVSSQ
B15
PLLVDD_18
H11
PLLVSS
G11
VDDR3
G9
XTALIN
A4
XTALOUT
B4
EXT_MEM_CLK
A3
SYSCLK
A8
SYSCLK#
B8
AGPCLKIN
B3
HCLKIN#
B5
ALINK_CLK
D8
AGPCLKOUT
B2
USBCLK
D7
REF27
B7
SYS_FBCLKOUT
B6
OSC
C5
SYS_FBCLKOUT#
A6
HCLKIN
A5
C525
0.1U_0402_16V4Z
1
2
L59
FBM-11-160808-121-T_0603
1 2
R1055
4.7K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C68
10U_0805_10V4Z
L63
KC FBM-L11-201209-221LMAT_0805
1 2
R67 M9@0_0402_5%
1 2
R71 M9@0_0402_5%
1 2
C92
10U_0805_10V4Z