ARTICLE
Copyright © 2020 by American Scientific Publishers
All rights reserved.
Printed in the United States of America
Journal of
Nanoelectronics and Optoelectronics
Vol. 15, pp. 142–146, 2020
www.aspbs.com/jno
Degeneration of Line-Edge Roughness-Induced
Variability for Dual-Metal Gate Fin
Field-Effect Transistors
Liang Dai and Wei-Feng Lü
∗
W e investigate, for the first time, the effect of line-edge roughness (LER)-induced variability for dual-metal
gate (DMG) Fin field-effect transistors (FinFETs) using a computer-aided-design simulation. The Gaussian
autocorrelation function is utilized for generating the LER sequence. From the standard deviations of sub-
threshold swing (SS), threshold voltage (V
TH
), and transconductance (g
m
), the simulation results indicate that
the LER-induced electrostatic integrity variability is related to the ratio of control gate to total gate lengths.
The variability caused by LER degrades with respect to the length of control gate near the source. Our work
fills a gap in the study of LER-induced v ariability for DMG FinFETs, and suggests that the length of the control
gate near the source should be greater than or equal to the screen gate near the drain in the entire gate.
Keywords: Line-Edge Roughness (LER), Fin Field-Effect Transistor (FinFET), Dual-Metal Gate (DMG).
1. INTRODUCTION
As metal-oxide-semiconductor field-effect transistor
(MOSFET) dimensions scale down to sub-22 nm applica-
tions, device variability due to line-edge roughness (LER)
has become a serious problem [1–6]. At the same time,
undesirable short channel effects (SCEs) have led to other
limitations on device performance [2, 7–9]. Therefore, the
Fin field-effect transistor (FinFET) has become one of
the most promising devices for future technology needs
because of its better resistance to SCEs [7, 8, 10]. In addi-
tion, the structure of dual-metal gates (DMG; that is, the
control gate M1 near the source, and the screen gate M2,
near the drain) has been explored to further improve the
performance [11–13]. Compared with the conventional
single metal gate (SMG) structure processing procedure,
the DMG devices require only additional processing
steps to laterally form two well-controlled gates [11, 14].
Meanwhile, by adjusting the channel potential and electric
field distributions along the channel, the DMG tran-
sistor has several advantages over conventional SMG
Key Laboratory for RF Circuits and Systems (Hangzhou Dianzi
University), Ministry of Education, Hangzhou 310018, China
∗
Author to whom correspondence should be addressed.
Email: lvwf@hdu.edu.cn
Recei ved: 25 June 2019
Accepted: 9 October 2019
counterparts: improved transconductance (g
m
) and better
carrier transport efficiency [12, 15, 16].
However, the effects of LER have been studied only
for SMG transistors. No research exists concerning the
effects of LER on DMG transistors. We therefore investi-
gate, for the first time, the performance variability caused
by LER with DMG FinFETs. We also explore the effects
of the length of the control gate near the source to that
of the entire gate on LER-induced performance variability.
Therefore, our study provides an optimized reference for
the proportion of the two metals in DMG FinFET design.
2. DEVICE STRUCTURE AND SIMULATION
Figures 1(a) and (b) give a bird’s eye and top views of
LER of the n-channel DMG FinFET studied here. Table I
shows detailed device parameters for this DMG FinFET.
According to DMG requirements, the DMG FinFET here
has two different gate metals, M1 and M2, with work func-
tions (WFs) assigned to be 4.62 eV, near the source and
4.205 eV near the drain, corresponding to the WN and
TaN [17], respectively. Figure 1(c) shows a cross-section
along the channel of the DMG FinFET [18].
To investigate the variability effects caused by LER in
the DMG FinFET, we set the ratio of the gate lengths
(L
1
/L) to 0, 0.2, 0.4, 0.6, 0.8, and 1 with gate-to-source
voltage (V
GS
) varying fr om 0 to 1 V at a dra in voltage
(V
DS
) of 50 mV. In addition, it should b e noted that WN
142 J. Nanoelectron. Optoelectron. 2020, Vol. 15, No. 1 1555-130X/2020/15/142/005 doi:10.1166/jno.2020.2727