TMS320F2812 DSP技术手册：高性能静态CMOS处理器

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"TMS320F2812是一款高性能的数字信号处理器，由Texas Instruments（TI）公司生产。该芯片以其强大的处理能力和丰富的内存配置在嵌入式系统领域广泛应用。" TMS320F2812是TI公司推出的基于C28x内核的数字信号处理器（DSP），其主要特点包括： 1. 高性能静态CMOS技术：TMS320F2812拥有150MHz的工作频率，意味着每个周期时间为6.67ns，能提供高效的计算能力。 2. 低功耗设计：支持1.8V核心电压和3.3V输入/输出电压，旨在降低系统的整体能耗。 3. 高性能CPU：C28x内核支持16x16和32x32乘加操作，还配备了一个16x16双MAC单元。其哈佛总线架构、原子操作、快速中断响应和处理能力使其在实时处理任务中表现出色。 4. 统一内存编程模型：具备4M线性程序地址空间和4G线性数据地址空间，代码效率高，兼容TMS320F24x/LF240x处理器的源代码。 5. 内置内存：最多128Kx16位的Flash存储器，分8个4K和6个16K扇区，2Kx16位一次性可编程只读存储器（OTPROM），以及不同类型的RAM，如L0和L1的4Kx16单访问RAM，H0的8Kx16 RAM，M0和M1的1Kx16 RAM。 6. 启动ROM：4Kx16位的启动ROM，包含软件启动模式和标准数学表。 7. 外部接口：F2812可以支持最大1.5M的总内存，具有可编程的等待状态、读写 strobe 时序，以及四个独立的芯片选择信号，提供了灵活的扩展能力。 8. 时钟和系统控制：动态PLL比率变化支持，使得系统时钟管理更加灵活，可以根据应用需求进行优化。这款芯片广泛应用于工业自动化、电力电子、电机控制、汽车电子、通信系统等领域，它的高效性能和灵活配置使其成为许多嵌入式应用的理想选择。TMS320F2812的用户可以从其强大的处理能力、低功耗特性和易于扩展的特性中受益，从而实现复杂信号处理任务的高效解决。

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description

The TMS320F2810 and TMS320F2812 devices, members of the TMS320C28x DSP generation, are highly

integrated, high-performance solutions for demanding control applications. The functional blocks and the

memory maps are described in subsequent paragraphs.

C28x CPU

The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is source

code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant software

investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop not only

their system control software in a high-level language, but also enables math algorithms to be developed using

C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by

microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x

32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle

higher numerical resolution problems that would otherwise demand a more expensive floating-point processor

solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a

device that is capable of servicing many asynchronous events with minimal latency. The C28x has an

8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute

at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware

minimizes the latency for conditional discontinuities. Special store conditional operations further improve

performance.

memory bus (Harvard bus architecture)

As with many DSP type devices, multiple busses are used to move data between the memories and peripherals

and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write

bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses

consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit

operations. The multiple bus architecture, commonly termed “Harvard Bus”, enables the C28x to fetch an

instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached

to the memory bus will prioritize memory accesses. Generally, the priority of Memory Bus accesses can be

summarized as follows:

Highest: Data Writes

†

Program Writes

†

Data Reads

Program Reads

‡

Lowest: Fetches

‡

peripheral bus

To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the F2810

and F2812 adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes

the various busses that make up the processor “Memory Bus” into a single bus consisting of 16 address lines

and 16 or 32 data lines and associated control signals. There are two versions of the peripheral bus supported

on the F2810 and F2812. One version only supports 16-bit accesses (called peripheral frame 2) and this retains

compatibility with C240x compatible peripherals. The other version supports both 16- and 32-bit accesses

(called peripheral frame 1) and is used to connect peripherals requiring higher throughput.

T PREVIEW

TMS320C28x, C28x, and TMS320C2000 are trademarks of Texas Instruments.

†

Simultaneous Data and Program writes cannot occur on the Memory Bus.

‡

Simultaneous Program Reads and Fetches cannot occur on the Memory Bus.

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

real-time JTAG and analysis

The C28x implements the standard IEEE 1149.1 JTAG interface. Additionally, the C28x supports real-time mode

of operation whereby the contents of memory, peripheral and register locations can be modified while the

processor is running and executing code and servicing interrupts. The user can also single step through

non-time critical code while enabling time-critical interrupts to be serviced without interference. The C28x

implements the real-time mode in hardware within the CPU. This is a unique feature to the C28x, no software

monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware

breakpoint or data/address watch-points and generate various user selectable break events when a match

occurs.

external interface (XINTF) (F2812 only)

This asynchronous interface consists of 19 address lines, 16 data lines, and four chip-select lines. The

chip-select lines are mapped to five external zones, Zone 0, 1, 2, 6, and 7. Zones 6 and 7 share a single

chip-select. Each of the five zones can be programmed with different number of wait states, strobe signal setup

and hold timing and each zone can be programmed for extending wait states externally or not. The

programmable wait-state, chip-select and programmable strobe timing enables glueless interface to external

memories and peripherals.

flash

The F2812 contains 128K x16 of embedded Flash memory and 2K x16 of OTP memory. The Flash memory

is segregated into eight 4K x16 sized sectors, and six 16K x16 sized sectors. The user can individually erase,

program and validate a sector while leaving other sectors untouched. Special memory pipelining is provided

to enable the Flash module to achieve higher performance. The Flash/OTP is mapped to both program and data

space hence can be used to execute code or store data information.

The F2810 has 64K x 16 of embedded Flash and 2K x 16 of OTP memory.

M0, M1 SARAMs

All C28x devices will contain these two blocks of single access memory, each 1Kx16 in size. The stack pointer

points to the beginning of block M1 on reset. The M0 block overlaps the 240x device B0, B1, B2 RAM blocks

and hence the mapping of data variables on the 240x devices can remain at the same physical address on C28x

devices. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program

and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is

performed within the linker. The C28x device presents a unified memory map to the programmer. This makes

for easier programming in high-level languages.

L0, L1, H0 SARAMs

The F2810 and the F2812 will contain an additional 16K x 16 of single-access RAM, divided into 3 blocks

(4K + 4K + 8K). Each block can be independently accessed hence minimizing pipeline stalls. Each block is

mapped to both program and data space.

boot ROM

The Boot ROM is factory programmed with boot loading software. Boot-mode signals are provided to tell the

boot loader software, programmed into the Boot ROM, what boot mode to use on power up. The user can select

to boot normally or to download new software from an external connection or to select boot software that is

programmed in the internal Flash. The Boot ROM will also contain standard tables, such as SIN/COS

waveforms, for use in math related algorithms.

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

security

The F2810 and F2812 support high levels of security to protect the user firmware from being reversed

engineered. The security features a 128-bit password, which the user programs into the Flash. One code

security module (CSM) is used to protect the Flash/OTP and the L0/L1 SARAM blocks. The security feature

prevents unauthorized users from examining the memory contents via the JTAG port, executing code from

external memory or trying to boot-load some undesirable software that would export the secure memory

contents. To enable access to the secure blocks, the user must write the correct 128-bit ”KEY” value, which

matches the value stored in the password locations within the Flash.

Code Security Module Disclaimer

The Code Security Module (“CSM”) included on this device was designed to password

protect the data stored in the associated memory (either ROM or Flash) and is warranted

by Texas Instruments (TI), in accordance with its standard terms and conditions, to

conform to TI’s published specifications for the warranty period applicable for this device.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE

COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE

ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS.

MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR

REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,

INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR

A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,

INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING

IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT

TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED

DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF

GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER

ECONOMIC LOSS.

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

peripheral interrupt expansion (PIE) block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block

can support up to 96 peripheral interrupts. On the F2810/F2812, 45 of the possible 96 interrupts are used by

peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into one of 12 CPU interrupt

lines (INT1

to INT12). Each of the 96 interrupts is, supported by its own vector stored in a dedicated RAM block

that can be overwritten by the user. The vector is, automatically fetched by the CPU on servicing the interrupt.

It takes 9 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly

respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual

interrupt can be enabled/disabled within the PIE block.

external interrupts (XINT1, 2, 13, XNMI)

The F2810 and F2812 support three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one

non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts can

be selected for negative or positive edge triggering and can also be enabled/disabled (including the XNMI). The

masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge

is detected. This counter can be used to accurately time stamp the interrupt.

oscillator and PLL

The F2810 and F2812 can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator

circuit. A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed

on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is

desired. The PLL block can be set in bypass mode.

watchdog

The F2810 and F2812 support a watchdog timer. The user software must regularly reset the watchdog counter

within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can

be disabled if necessary.

peripheral clocking

The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a

peripheral is not in use. Additionally, the system clock to the serial ports and the event managers, CAP and QEP

blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from

increasing CPU clock speeds.

low-power modes

The F2810 and F2812 devices are full static CMOS devices. Three low-power modes are provided:

IDLE: Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only

those peripherals that need to function during IDLE are left operating. An enabled interrupt

from an active peripheral will wake the processor from IDLE mode.

STANDBY: Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.

An external interrupt event will wake the processor and the peripherals. Execution begins on

the next valid cycle after detection of the interrupt event.

HALT: Turn off oscillator. This mode basically shuts down the device and places it in the lowest

possible power consumption mode. Only a reset or XNMI will wake the device from this mode.

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

peripheral frames 0, 1, 2 (PFn)

The F2810 and F2812 segregate peripherals into three sections. The mapping of peripherals is as follows:

PF0: XINTF: External Interface Configuration Registers

PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash: Flash Control, Programming, Erase, Verify Registers

Timers: CPU-Timers 0, 1, 2 Registers

CSM: Code Security Module KEY Registers

PF1: eCAN: eCAN Mailbox and Control Registers

PF2: SYS: System Control Registers

GPIO: GPIO Mux Configuration and Control Registers

EV: Event Manager (EVA/EVB) Control Registers

McBSP: McBSP Control and TX/RX Registers

SCI: Serial Communications Interface (SCI) Control and RX/TX Registers

SPI: Serial Peripheral Interface (SPI) Control and RX/TX Registers

ADC: 12-Bit ADC Registers

general-purpose input/output (GPIO) multiplexer

Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the user

to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured as

inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal mode. For specific

inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches.

32-bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The

timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The

counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter

reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timers 1 and 2 are reserved for

Real-Time OS (RTOS) applications. CPU-Timer 2 is connected to INT14 of the CPU. CPU-Timer 1 can be

connected to INT13 of the CPU. CPU-Timer 0 is for general use and is connected to the PIE block.

motor control peripherals

The F2810 and F2812 support the following peripherals which, are used for controlling motors:

EV: The event manager module includes general-purpose timers, full-compare/PWM units,

capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event

managers are provided which enable two three-phase motors to be driven or four two-phase

motors. The event managers on the F2810 and F2812 are compatible to the event managers

on the 240x devices (with some minor enhancements).

ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It will contain two

sample-and-hold units for simultaneous sampling.

T PREVIEW

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