16 Datasheet
14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) .......................... 599
14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)................................ 600
14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2).................................................................................601
14.2.4 AIR—AHCI Index Register (D31:F2) ........................................................601
14.2.5 AIDR—AHCI Index Data Register (D31:F2)...............................................601
14.3 Serial ATA Index/Data Pair Superset Registers..................................................... 602
14.3.1 SINDX—Serial ATA Index Register (D31:F2)............................................. 602
14.3.2 SDATA—Serial ATA Data Register (D31:F2) .............................................. 603
14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2) .............................603
14.3.2.2 PxSCTL—Serial ATA Control Register (D31:F2) ............................ 604
14.3.2.3 PxSERR—Serial ATA Error Register (D31:F2)...............................605
14.4 AHCI Registers (D31:F2) .................................................................................. 606
14.4.1 AHCI Generic Host Control Registers (D31:F2).......................................... 607
14.4.1.1 CAP—Host Capabilities Register (D31:F2) ................................... 607
14.4.1.2 GHC—Global PCH Control Register (D31:F2) ............................... 609
14.4.1.3 IS—Interrupt Status Register (D31:F2) ...................................... 610
14.4.1.4 PI—Ports Implemented Register (D31:F2) .................................. 611
14.4.1.5 VS—AHCI Version Register (D31:F2).......................................... 612
14.4.1.6 EM_LOC—Enclosure Management Location Register (D31:F2)........ 612
14.4.1.7 EM_CTRL—Enclosure Management Control Register (D31:F2)........612
14.4.1.8 CAP2—HBA Capabilities Extended Register.................................. 613
14.4.1.9 RSTF—Intel
®
RST Feature Capabilities Register ...........................614
14.4.2 Port Registers (D31:F2).........................................................................616
14.4.2.1 PxCLB—Port [5:0] Command List Base Address Register
(D31:F2)................................................................................ 619
14.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper
32-Bits Register (D31:F2) ........................................................619
14.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2) .................. 619
14.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits
Register (D31:F2) ................................................................... 620
14.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2) ....................620
14.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2) ....................622
14.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2) .........................623
14.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2)..................... 626
14.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2) ........................... 626
14.4.2.10PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2) .............. 627
14.4.2.11PxSCTL — Port [5:0] Serial ATA Control Register (D31:F2) ........... 628
14.4.2.12PxSERR—Port [5:0] Serial ATA Error Register (D31:F2) ................ 629
14.4.2.13PxSACT—Port [5:0] Serial ATA Active Register (D31:F2)............... 631
14.4.2.14PxCI—Port [5:0] Command Issue Register (D31:F2) ....................631
15 SATA Controller Registers (D31:F5) ....................................................................... 633
15.1 PCI Configuration Registers (SATA–D31:F5) ........................................................ 633
15.1.1 VID—Vendor Identification Register (SATA—D31:F5) ................................. 634
15.1.2 DID—Device Identification Register (SATA—D31:F5) ................................. 634
15.1.3 PCICMD—PCI Command Register (SATA–D31:F5) ..................................... 635
15.1.4 PCISTS — PCI Status Register (SATA–D31:F5) ......................................... 636
15.1.5 RID—Revision Identification Register (SATA—D31:F5) ............................... 636
15.1.6 PI—Programming Interface Register (SATA–D31:F5) ................................. 637
15.1.7 SCC—Sub Class Code Register (SATA–D31:F5) .........................................637
15.1.8 BCC—Base Class Code Register
(SATA–D31:F5SATA–D31:F5)................................................................. 637
15.1.9 PMLT—Primary Master Latency Timer Register
(SATA–D31:F5) ....................................................................................638
15.1.10PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F5)........................................................................ 638
15.1.11PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F5) ....................................................................................638
15.1.12SCMD_BAR—Secondary Command Block Base Address
Register (SATA D31:F5) ........................................................................639
15.1.13SCNL_BAR—Secondary Control Block Base Address
Register (SATA D31:F5) ........................................................................639
15.1.14BAR — Legacy Bus Master Base Address Register
(SATA–D31:F5) ....................................................................................640
15.1.15SIDPBA — SATA Index/Data Pair Base Address Register
(SATA–D31:F5) ....................................................................................640
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