BCM5396：单芯片16端口Gigabit Ethernet交换器数据手册

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"BCM5396交换芯片数据手册" BCM5396是一款专为嵌入式系统设计的单芯片16端口串行千兆以太网交换器，其核心功能是提供低功耗、高性能的桌面交换解决方案或Web智能应用。这款芯片由博通（Broadcom）公司制造，具有以下主要特点： 1. 16个1.25G SerDes/SGMII接口：BCM5396集成了16个1.25Gbps的串行收发器（SerDes）/简化的千兆媒体独立接口（SGMII）端口，这些接口可以连接到外部的千兆物理层（PHY）设备或光纤模块，极大地减少了板级空间的需求。 2. 高度集成：该芯片将高速交换系统的所有功能集成在一起，包括报文缓冲区、媒体访问控制器（MACs）、地址管理以及无阻塞交换控制器，所有这些都封装在一枚0.13微米的CMOS器件中。这样的设计降低了物料成本，简化了系统复杂性。 3. 符合标准：BCM5396遵循IEEE 802.3系列标准，包括802.3、802.3u、802.3ab和802.3x，确保与所有行业标准的以太网、快速以太网和千兆以太网设备兼容。此外，它支持MAC控制PAUSE帧和自动协商子部分，提供了流控功能。 4. 无阻塞交换：BCM5396的无阻塞交换控制器确保了所有端口间的通信不会因内部资源冲突而受到影响，提供了线速交换能力，即所有端口同时以全千兆速率传输数据时，仍能保持高效运行。 5. 电源效率与散热：考虑到嵌入式应用的电源和热管理要求，BCM5396设计时考虑了低功耗特性，这使得它在提供高性能的同时，能够适应各种环境，特别是对电源和散热有严格要求的场景。 6. 扩展功能：除基本的交换功能外，BCM5396可能还包含其他高级特性，如QoS（服务质量）、VLAN（虚拟局域网）支持、端口镜像、IGMP（互联网组管理协议）监听等，以满足企业网络管理和网络安全的需求。 BCM5396交换芯片是嵌入式网络设备设计中的理想选择，它在提供高密度、高性能千兆以太网交换能力的同时，兼顾了成本效益和设计简洁性。其广泛的应用场景包括桌面交换机、企业级路由器、网络存储设备以及工业自动化和物联网设备。通过利用这种芯片，开发者可以构建出功能强大且成本优化的网络基础设施。

3/6/2012 PJ87F

List of Figures BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch



February 07, 2012 • 5396-DS113-R Page 16

Figure 36: SPI Timings, SS Asserted During SCK Low ......................................................................................190

Figure 37: EEPROM Timing.............................................................................................................................191

Figure 38: 256-Pin FBGA Package Outline Drawing........................................................................................193

3/6/2012 PJ87F

List of Tables BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch



February 07, 2012 • 5396-DS113-R Page 17

List of Tables

Table 1: Frame Priority Decision Tree Summary ..............................................................................................29

Table 2: Bucket Bit Rate ...................................................................................................................................33

Table 3: Unicast Forward Field Definitions.......................................................................................................39

Table 4: Address Table Entry for Unicast Address............................................................................................39

Table 5: Multicast Forward Field Definitions ...................................................................................................41

Table 6: Address Table Entry for Multicast ARL Address..................................................................................41

Table 7: Behavior for Reserved Multicast Addresses.......................................................................................42

Table 8: Spanning Tree State............................................................................................................................47

Table 9: SGMII and SerDes Auto-Negotiation ..................................................................................................54

Table 10: Transmit/Receive Frame Format Over Management Port ...............................................................56

Table 11: OPCODE Field in BRCM Tag for Management Port Frame ...............................................................57

Table 12: IMP Broadcom TAG RX from CPU .....................................................................................................57

Table 13: IMP Broadcom TAG TX to CPU..........................................................................................................58

Table 14: EEPROM_EXT[1:0] Settings...............................................................................................................64

Table 15: EEPROM Header Format...................................................................................................................65

Table 16: EEPROM Contents ............................................................................................................................65

Table 17: Pseudo-PHY MII Register Definitions................................................................................................71

Table 18: MII Management Frame Format ......................................................................................................72

Table 19: Serial LED Mode Matrix ....................................................................................................................73

Table 20: Serial LED Status Types .....................................................................................................................74

Table 21: Load Meter LED Decode ...................................................................................................................74

Table 22: I/O Signal Type Definitions ...............................................................................................................76

Table 23: Signal Descriptions............................................................................................................................77

Table 24: Pin Assignment (Listed by Pin Number) ...........................................................................................83

Table 25: Pin Assignment (Listed by Signal Name)...........................................................................................85

Table 26: Global Page Register Map.................................................................................................................88

Table 27: Control Registers (Page 00h) ............................................................................................................91

Table 28: 10/100/1000 Port Control Register (Page 00h: Address 00h–0Fh) ..................................................93

Table 29: IMP Port Control Register (Page 00h: Address 10h).........................................................................93

Table 30: Switch Mode Register (Page 00h: Address 20h)...............................................................................94

Table 31: LED A Register (Page 00h: Address 24h–25h)...................................................................................95

Table 32: New Control Register (Page 00h: Address 3Bh) ...............................................................................95

Table 33: Reserved Multicast Register (Page 00h: Address 50h) .....................................................................96

Table 34: Load Meter Update Rate Control Register (Page 00h: Address 51h) ...............................................96

Table 35: Unicast Lookup Failed Forward Map Register (Page 00h: 54h–57h)................................................97

3/6/2012 PJ87F

List of Tables BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch



February 07, 2012 • 5396-DS113-R Page 18

Table 36: Multicast Lookup Failed Forward Map Register (Page 00h: Address 58h–5Bh)...............................97

Table 37: Port N State Override Register (Page 00h: Address 60–6Fh)............................................................97

Table 38: Port 16 (IMP) State Override Register (Page 00h: Address 70h) ......................................................98

Table 39: 802.1X Control Register 1 (Page 00h: Address 77h) .........................................................................99

Table 40: 802.1X Control Register 2 (Page 00h: Address 78h–7Bh).................................................................99

Table 41: SerDes Default Values Register (Page 00h: Address 80h–83h) ........................................................99

Table 42: SerDes Select Early Version of CRS and COL Register (Page 00h: Address 84h–85h).....................100

Table 43: External PHY Scan Control Register (Page 00h: Address 86h) ........................................................100

Table 44: Fast Aging Control Register (Page 00h: Address 88h) ....................................................................100

Table 45: Fast Aging Port Register (Page 00h: Address 89h)..........................................................................101

Table 46: Fast Aging VID Register (Page 00h: Address 138d–139d, 8Ah–8Bh) ..............................................101

Table 47: Pause Frame Detection Control Register (Page 00h: Address 90h)................................................101

Table 48: Status Registers (Page 01h) ............................................................................................................102

Table 49: Link Status Summary Register (Page 01h: Address 00h–03h) ........................................................103

Table 50: Link Status Change Register (Page 01h: Address 04h–07h)............................................................103

Table 51: Port Speed Summary Register (Page 01h: Address 08h–0Fh) ........................................................103

Table 52: Duplex Status Summary Register (Page 01h: Address 10h–13h) ...................................................104

Table 53: TX PAUSE Status Summary Register (Page 01h: Address 14h–17h) ...............................................104

Table 54: RX PAUSE Status Summary Register (Page 01h: Address 18h–1Bh)...............................................104

Table 55: Port N PHY Status Register (Page 01h: Address 20–2Fh)................................................................105

Table 56: SerDes Signal Detect Status Register (Page 01h: Address 40h)......................................................105

Table 57: BIST Status Register (Page 01h, Address 46h) ................................................................................105

Table 58: Strap Value Register (Page 01h: Address 70h–73h) .......................................................................106

Table 59: Management Mode Registers (Page 02h) ......................................................................................106

Table 60: Global Management Configuration Register (Page 02h: Address 00h) ..........................................107

Table 61: Aging Time Control Register (Page 02h: Address 0Ch–0Fh) ...........................................................107

Table 62: Mirror Capture Control Register (Page 02h: Address 10h–11h).....................................................108

Table 63: Ingress Mirror Control Register (Page 02h: Address 12h–15h) ......................................................108

Table 64: Ingress Mirror Divider Register (Page 02h: Address 16h–17h).......................................................109

Table 65: Egress Mirror Control Register (Page 02h: Address 1Ch–1Fh) .......................................................109

Table 66: Model ID Register (Page 02h: Address 30h) ...................................................................................110

Table 67: Revision ID Register (Page 02h: Address 40h) ................................................................................110

Table 68: ARL Control Registers (Page 04h) ...................................................................................................110

Table 69: Global ARL Configuration Register (Page 04h: Address 00h)..........................................................110

Table 70: BPDU Multicast Address Register (Page 04h: Address 04h–09h)...................................................111

Table 71: Multiport Address 1 Register (Page 04h: Address 10h–15h)..........................................................111

3/6/2012 PJ87F

List of Tables BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch



February 07, 2012 • 5396-DS113-R Page 19

Table 72: Multiport Vector 1 Register (Page 04h: Address 16h–19h)............................................................112

Table 73: Multiport Address 2 Register (Page 04h: Address 20h–25h)..........................................................112

Table 74: Multiport Vector 2 Register (Page 04h: Address 26h–29h)............................................................112

Table 75: ARL/VLAN Access Registers (Page 05h) ..........................................................................................113

Table 76: ARL Read/Write Control Register (Page 05h: Address 00h) ...........................................................114

Table 77: MAC Address Index Register (Page 05h: Address 02h–07h) ..........................................................114

Table 78: VID Index Register (Page 05h: Address 08h–09h) ..........................................................................115

Table 79: ARL MAC/VID Entry 0 Register (Page 05h: Address 10h–17h) .......................................................115

Table 80: ARL FWD Entry 0 Register (Page 05h: Address 18h–1Bh)...............................................................115

Table 81: ARL MAC/VID Entry 1 Register (Page 05h: Address 20h–27h) .......................................................116

Table 82: ARL FWD Entry 1 Register (Page 05h: Address 28h–2Bh)...............................................................117

Table 83: ARL Search Control Register (Page 05h: Address 30h) ...................................................................118

Table 84: ARL Search Address Register (Page 05h: Address 31h–32h) ..........................................................119

Table 85: ARL Search MAC/VID Result Register 0 (Page 05h: Address 33h–3Ah) ..........................................119

Table 86: ARL Search Result Register 0 (Page 05h: Address 3Bh–3Eh) ..........................................................119

Table 87: ARL Search MAC/VID Result Register 1 (Page 05h: Address 40h–47h) ..........................................120

Table 88: ARL Search Result Register 1 (Page 05h: Address 48h–4Bh) ..........................................................120

Table 89: VLAN Table Read/Write Control Register (Page 05h: Address 60h)...............................................122

Table 90: VLAN Table Address Index Register (Page 05h: Address 61h–62h)................................................122

Table 91: VLAN Table Entry Register (Page 05h: Address 63h–6Ah)..............................................................122

Table 92: Flow Control Registers (Page 0Ah) .................................................................................................123

Table 93: Internal SerDes Registers Page Descriptions 10h–1Fh ...................................................................127

Table 94: Internal SerDes Registers Page 10h–1Fh ........................................................................................127

Table 95: MII Control (Page 10h–1Fh: Address 00h–01h)..............................................................................129

Table 96: MII Status (Page 10h–1Fh: Address 02h–03h)................................................................................130

Table 97: Auto-Negotiation Advertisement (Page 10h–1Fh: Address 08h–09h) ...........................................131

Table 98: Auto-Negotiation Link Partner Ability (Page 10h–1Fh: Address 0Ah–0Bh) ....................................132

Table 99: Auto-Negotiation Expansion (Page 10h–1Fh: Address 0Ch–0Dh) ..................................................133

Table 100: Extended Status (Page 10h–1Fh: Address 1Eh–1Fh) ....................................................................133

Table 101: SerDes/SGMII Control1 (Page 10h–1Fh: Address 20h–21h, Block 0) ...........................................134

Table 102: Analog Transmit Register (Page 10h ~ 1Fh: Address 20h ~ 21h, Block 1).....................................136

Table 103: SerDes/SGMII Control 2 (Page 10h–1Fh: Address 22h–23h)........................................................136

Table 104: SerDes/SGMII Control 3 (Page 10h–1Fh: Address 24h–25h)........................................................137

Table 105: SerDes/SGMII Status 1 (Page 10h–1Fh: Address 28h–29h)..........................................................138

Table 106: SerDes/SGMII Status 2 (Page 10h–1Fh: Address 2Ah–2Bh) .........................................................139

Table 107: SerDes/SGMII Status 3 (Page 10h–1Fh: Address 2Ch–2Dh) .........................................................140

3/6/2012 PJ87F

List of Tables BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch



February 07, 2012 • 5396-DS113-R Page 20

Table 108: BER/CRC Error Counter Register (Page 10h ~ 1Fh: Address 2Eh ~ 2Fh) .......................................141

Table 109: PRBS Control Register (Page 10h ~ 1Fh: Address 30h ~ 31h) .......................................................142

Table 110: PRBS Status Register (Page 10h ~ 1Fh: Address 32h ~ 33h) .........................................................142

Table 111: Pattern Generator Control Register (Page 10h ~ 1Fh: Address 34h ~ 35h)..................................143

Table 112: Pattern Generator Control Register (Page 10h ~ 1Fh: Address 36h ~ 37h)..................................144

Table 113: Pattern Generator Control Register (Page 10h ~ 1Fh: Address 36h ~ 37h)..................................144

Table 114: Force Transmit 1 Register (Page 10h ~ 1Fh: Address 3Ah ~ 3Bh) .................................................145

Table 115: Block Address (Pages 10h–1Fh: Address 3Eh ~ 3Fh) ....................................................................145

Table 116: QoS Registers (Page 30h)..............................................................................................................145

Table 117: QoS Global Control Register (Page 30h: Address 00h) .................................................................147

Table 118: QoS Threshold Control Register (Page 30h: Address 01h–02h) ...................................................147

Table 119: QoS 1P Enable Register (Page 30h: Address 04h–07h) ................................................................147

Table 120: QoS DiffServ Enable Register (Page 30h: Address 08h–0Bh)........................................................148

Table 121: 1P/1Q Priority Map Register (Page 30h: Address 10h–13h).........................................................148

Table 122: DiffServ Priority Map 0 Register (Page 30h: Address 30h–35h) ...................................................149

Table 123: DiffServ Priority Map 1 Register (Page 30h: Address 36h–3Bh) ...................................................149

Table 124: DiffServ Priority Map 2 Register (Page 30h: Address 3Ch–41h) ...................................................150

Table 125: DiffServ Priority Map 3 Register (Page 30h: Address 42h–47h) ...................................................151

Table 126: QoS Port Control N Register (Page 30h: Address 50h–71h) .........................................................152

Table 127: QoS TX Control Register (Page 30h: Address 80h)........................................................................153

Table 128: Queue N Weight Register (Page 30h: Address 81h–84h) .............................................................153

Table 129: EtherType Priority Control Register (Page 30h: Address 88h–8Bh)..............................................153

Table 130: Enable Traffic Priority Remap Control Register (Page 30h: Address A0h–A3h) ...........................154

Table 131: Traffic Priority Remap Register (Page 30h: Address A4h) ............................................................154

Table 132: Page 31h Port-based VLAN Registers ...........................................................................................154

Table 133: Port VLAN Control Register (Pages: 31h, Address 0h–43h)..........................................................155

Table 134: Trunking Registers (Page 32h) ......................................................................................................155

Table 135: MAC Trunk Control Register (Pages: 32h, Address 1h) ................................................................157

Table 136: Trunk Group Register [0:3] (Pages: 32h, Address 90h–9Fh).........................................................158

Table 137: QoS Registers (Page 34h)..............................................................................................................158

Table 138: Global Control 0 Register (Pages 34h: Address 00h) ....................................................................159

Table 139: Global Control 1 Register (Pages 34h: Address 01h) ....................................................................159

Table 140: Global Control 2 Register (Pages 34h: Address 02h) ....................................................................160

Table 141: Global Control 3 Register (Pages 34h: Address 03h–06h) ............................................................161

Table 142: Global Control 4 Register (Pages 34: Address 07h) ......................................................................161

Table 143: Global Control 5 Register (Pages 34h: Address 08h) ....................................................................161

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BCM5396：单芯片16端口Gigabit Ethernet交换器数据手册

16口千兆交换机芯片BCM5396 Data Sheet 数据手册

BCM5396_bcm5396datasheet_bcm5396_switch

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