TI公司TMS320DM6467T数字媒体系统级芯片数据手册

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"TMS320DM6467T是德州仪器（TI）公司推出的一款高性能数字媒体系统级芯片（DMSoC），主要应用于多媒体处理领域。该芯片集成了C64x+ DSP核心和ARM926EJ-S处理器，具有强大的处理能力和丰富的功能特性。" TMS320DM6467T芯片的特点： 1. 高性能：该芯片内置了一个工作频率高达1GHz的C64x+ DSP核心，能提供每秒8000 MIPS的运算能力，适合处理复杂的数字信号处理任务。 2. 双核架构：除了C64x+ DSP，还包含一个500MHz的ARM926EJ-S内核，支持32位和16位（Thumb模式）指令集，适用于实时操作系统和应用处理。 3. 内存系统：配备了32KB的L1数据缓存（2路组关联）、128KB的L2统一映射内存/缓存，以及灵活的RAM/Cache分配机制，确保高效的数据存储和访问。 4. 高度并行：C64x+ DSP核心拥有八个高度独立的功能单元，每个时钟周期可以执行八条32位C64x+指令，支持单周期MAC操作，提高计算效率。 5. 扩展特性：支持DSP指令扩展，两个乘法器可进行四个16x16位乘法运算，增强了处理多媒体数据的能力。 6. 实时调试：内置嵌入式ICE-RT逻辑，用于实时调试，方便开发者进行软件开发和故障排查。 7. ARM Jazelle技术：利用ARM的Jazelle技术，可以加速Java字节码的执行，提高了嵌入式系统的运行效率。 8. 内存架构：遵循ARM9的内存架构，包括16KB的指令缓存和8KB的数据缓存，优化了代码执行和数据访问速度。 9. 工业级温度范围：提供工业温度版本，能够在恶劣环境下稳定工作。综上，TMS320DM6467T是一款高度集成、高性能的数字媒体处理芯片，适合于视频编码、解码、图像处理、网络通信等多种应用场景，是嵌入式系统设计中的理想选择。其强大的处理能力和灵活的内存管理机制，使得它在多媒体应用领域具有广泛的应用前景。

TMS320DM6467T

SPRS605A–JULY 2009–REVISED NOVEMBER 2009

www.ti.com

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a

pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data

performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2

comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit

which increases the performance of algorithms that do searching and sorting. Finally, to increase data

packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit

and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack

instructions return parallel results to output precision including saturation support.

Other new features include:

• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where

multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size

associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.

• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common

instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+

compiler can restrict the code to use certain registers in the register file. This compression is

performed by the code generation tools.

• Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit

multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field

multiplication.

• Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to

detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and

from system events (such as a watchdog time expiration).

• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a

basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with

read, write, and execute permissions.

• Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a

free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following

documents:

• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)

• TMS320C64x Technical Overview (literature number SPRU395)

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Product Folder Link(s): TMS320DM6467T

TMS320DM6467T

SPRS605A–JULY 2009–REVISED NOVEMBER 2009

www.ti.com

3.4.2 DSP Memory Mapping

The DSP memory map is shown in Section 3.5, Memory Map Summary. Configuration of the control

registers for DDR2, EMIFA, and ARM Internal RAM is supported by the ARM. The DSP has access to

memories shown in the following sections.

3.4.2.1 ARM Internal Memories

The DSP has access to the 32KB ARM Internal RAM on the ARM D-TCM interface (i.e., data only).

3.4.2.2 External Memories

The DSP has access to the following External memories:

• DDR2 Synchronous DRAM

• Asynchronous EMIF / NOR Flash

• ATA

3.4.2.3 DSP Internal Memories

The DSP has access to the following DSP memories:

• L2 RAM

• L1P RAM

• L1D RAM

3.4.2.4 C64x+ CPU

The C64x+ core uses a two-level cache-based architecture. The Level 1 Program memory/cache (L1P)

consists of 32 KB memory space that can be configured as mapped memory or direct mapped cache. The

Level 1 Data memory/cache (L1D) consists of 32 KB that can be configured as mapped memory or 2-way

set associated cache. The Level 2 memory/cache (L2) consists of a 128 KB RAM memory space that is

shared between program and data space. L2 memory can be configured as mapped memory, cache, or a

combination of both.

Table 3-2 shows a memory map of the C64x+ CPU cache registers for the device.

Table 3-2. C64x+ Cache Registers

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 0000 L2CFG L2 Cache configuration register

0x0184 0020 L1PCFG L1P Size Cache configuration register

0x0184 0024 L1PCC L1P Freeze Mode Cache configuration register

0x0184 0040 L1DCFG L1D Size Cache configuration register

0x0184 0044 L1DCC L1D Freeze Mode Cache configuration register

0x0184 0048 - 0x0184 0FFC - Reserved

0x0184 1000 EDMAWEIGHT L2 EDMA access control register

0x0184 1004 - 0x0184 1FFC - Reserved

0x0184 2000 L2ALLOC0 L2 allocation register 0

0x0184 2004 L2ALLOC1 L2 allocation register 1

0x0184 2008 L2ALLOC2 L2 allocation register 2

0x0184 200C L2ALLOC3 L2 allocation register 3

0x0184 2010 - 0x0184 3FFF - Reserved

0x0184 4000 L2WBAR L2 writeback base address register

0x0184 4004 L2WWC L2 writeback word count register

0x0184 4010 L2WIBAR L2 writeback invalidate base address register

0x0184 4014 L2WIWC L2 writeback invalidate word count register

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TMS320DM6467T

www.ti.com

SPRS605A–JULY 2009–REVISED NOVEMBER 2009

Table 3-2. C64x+ Cache Registers (continued)

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 4018 L2IBAR L2 invalidate base address register

0x0184 401C L2IWC L2 invalidate word count register

0x0184 4020 L1PIBAR L1P invalidate base address register

0x0184 4024 L1PIWC L1P invalidate word count register

0x0184 4030 L1DWIBAR L1D writeback invalidate base address register

0x0184 4034 L1DWIWC L1D writeback invalidate word count register

0x0184 4038 - Reserved

0x0184 4040 L1DWBAR L1D Block Writeback

0x0184 4044 L1DWWC L1D Block Writeback

0x0184 4048 L1DIBAR L1D invalidate base address register

0x0184 404C L1DIWC L1D invalidate word count register

0x0184 4050 - 0x0184 4FFF - Reserved

0x0184 5000 L2WB L2 writeback all register

0x0184 5004 L2WBINV L2 writeback invalidate all register

0x0184 5008 L2INV L2 Global Invalidate without writeback

0x0184 500C - 0x0184 5027 - Reserved

0x0184 5028 L1PINV L1P Global Invalidate

0x0184 502C - 0x0184 5039 - Reserved

0x0184 5040 L1DWB L1D Global Writeback

0x0184 5044 L1DWBINV L1D Global Writeback with Invalidate

0x0184 5048 L1DINV L1D Global Invalidate without writeback

0x0184 8000 - 0x0184 803C MAR0 - MAR15 Reserved (corresponds to byte address 0x0000 0000 - 0x0FFF FFFF)

Memory Attribute Registers for ARM TCM (corresponds to byte address

0x0184 8040 MAR16

0x1000 0000 - 0x10FF FFFF)

0x0184 8044 - 0x0184 80FC MAR17 - MAR63 Reserved (corresponds to byte address 0x1100 0000 - 0x3FFF FFFF)

0x0184 8100 MAR64 Reserved (corresponds to byte address 0x4000 0000 - 0x40FF FFFF)

0x0184 8104 MAR65 Reserved (corresponds to byte address 0x4100 0000 - 0x41FF FFFF)

Memory Attribute Registers for EMIFA (corresponds to byte address 0x4200

0x0184 8108 - 0x0184 8124 MAR66 - MAR73

0000 - 0x49FF FFFF)

0x0184 8128 - 0x0184 812C MAR74 - MAR75 Reserved (corresponds to byte address 0x4A00 0000 - 0x4BFF FFFF)

Memory Attribute Registers for VLYNQ (corresponds to byte address

0x0184 8130 - 0x0184 813C MAR76 - MAR79

0x4C00 0000 - 0x4FFF FFFF)

0x0184 8140 - 0x0184 81FC MAR80 - MAR127 Reserved (corresponds to byte address 0x5000 0000 - 0x7FFF FFFF)

Memory Attribute Registers for DDR2 (corresponds to byte address 0x8000

0x0184 8200 - 0x0184 82FC MAR128 - MAR191

0000 - 0xBFFF FFFF)

0x0184 8300 - 0x0184 83FC MAR192 - MAR255 Reserved (corresponds to byte address 0xC000 0000 - 0xFFFF FFFF)

3.4.3 Peripherals

The DSP has access/controllability of the following peripherals:

• HDVICP0/1

• EDMA

• McASP0/1

• 2 Timers (Timer0 and Timer1) that can each be configured as 1 64-bit or 2 32-bit timers

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