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Texas Instruments LM3S811 微控制器数据手册分享
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更新于2024-07-26
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"LM3S811是Texas Instruments(TI)公司生产的Stellaris系列微控制器的数据手册,属于官方发布的生产数据。该手册包含了产品的详细规格和技术信息,适用于产品开发和设计应用。"
Stellaris LM3S811是一款基于ARM Cortex-M3内核的32位微控制器,具有高性能、低功耗的特点。Cortex-M3是ARMLtd.设计的一种高效能、低成本的处理器核心,适合嵌入式应用。LM3S811在TI的Stellaris家族中扮演着重要的角色,提供了丰富的外设接口和内存配置,以满足不同领域的嵌入式系统需求。
数据手册通常会包含以下关键内容:
1. **技术规格**:包括CPU时钟速度、内存容量(Flash和RAM)、工作电压范围、I/O引脚数量等。LM3S811可能具有多个速度等级和封装选项,这些信息都会在手册中详细列出。
2. **内核特性**:Cortex-M3内核支持Thumb2指令集,提供高效的代码执行,并具有嵌套向量中断控制器(NVIC),可处理多级中断。
3. **外设集成**:LM3S811可能集成了多种外设,如串行通信接口(UART、SPI、I2C)、定时器、PWM、ADC、GPIO、CRC计算单元等,这些外设对于实现各种功能至关重要。
4. **电源管理**:介绍微控制器的低功耗模式和电源控制选项,如睡眠、待机和休眠模式,以及如何在不同状态下切换。
5. **封装和管脚配置**:提供微控制器的物理封装信息,包括管脚排列和功能描述,这对于硬件设计人员进行PCB布局非常重要。
6. **电气特性**:列出工作温度范围、ESD保护、噪声容限等电气参数,确保在实际应用中的可靠性。
7. **开发工具和软件支持**:TI可能提供了相应的开发工具链,如IDE、编译器、调试器,以及StellarisWare库,这是一系列预编译的软件组件,用于简化开发过程。
8. **应用示例和设计指南**:可能会包含一些基本的应用电路示例和设计建议,帮助开发者快速上手。
9. **质量与可靠性**:TI的产品符合其标准质保条款,但生产过程中不一定对所有参数进行测试。手册中会有关于产品在关键应用中的使用注意事项和免责声明。
10. **支持和资源**:TI通常会提供在线技术支持、产品信息中心链接等资源,帮助用户解决问题和获取最新信息。
"Datasheet-LM3S811"提供了关于LM3S811微控制器的全面技术信息,是开发基于此芯片的嵌入式系统的重要参考资料。对于电子工程师和嵌入式开发者来说,理解并充分利用这份数据手册的内容至关重要。
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 282
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 285
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 287
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 288
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 289
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 291
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 292
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 293
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 294
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 295
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 296
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 297
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 298
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 299
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 300
Watchdog Timer ........................................................................................................................... 301
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 305
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 306
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 307
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 308
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 309
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 310
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 311
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 312
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 313
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 314
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 315
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 316
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 317
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 318
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 319
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 320
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 321
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 322
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 323
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 324
Analog-to-Digital Converter (ADC) ............................................................................................. 325
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 334
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 335
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 336
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 337
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 338
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 339
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 343
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 344
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 346
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 347
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 348
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Table of Contents
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 350
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 353
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 353
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 353
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 353
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 354
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 354
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 354
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 354
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 355
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 355
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 356
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 356
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 358
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 359
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 360
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 361
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 368
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 370
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 372
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 374
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 375
Register 6: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 376
Register 7: UART Control (UARTCTL), offset 0x030 ......................................................................... 378
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 380
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 382
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 384
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 385
Register 12: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 386
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 388
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 389
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 390
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 391
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 392
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 393
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 394
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 395
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 396
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 397
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 398
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 399
Synchronous Serial Interface (SSI) ............................................................................................ 400
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 412
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 414
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 416
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 417
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 419
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 420
17January 09, 2011
Texas Instruments-Production Data
Stellaris® LM3S811 Microcontroller
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 422
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 423
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 424
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 425
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 426
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 427
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 428
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 429
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 430
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 431
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 432
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 433
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 434
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 435
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 436
Inter-Integrated Circuit (I
2
C) Interface ........................................................................................ 437
Register 1: I
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 452
Register 2: I
2
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 453
Register 3: I
2
C Master Data (I2CMDR), offset 0x008 ......................................................................... 457
Register 4: I
2
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 458
Register 5: I
2
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 459
Register 6: I
2
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 460
Register 7: I
2
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 461
Register 8: I
2
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 462
Register 9: I
2
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 463
Register 10: I
2
C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 465
Register 11: I
2
C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 466
Register 12: I
2
C Slave Data (I2CSDR), offset 0x808 ........................................................................... 468
Register 13: I
2
C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 469
Register 14: I
2
C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 470
Register 15: I
2
C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 471
Register 16: I
2
C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 472
Analog Comparator ..................................................................................................................... 473
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 477
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 478
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 479
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 480
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 481
Register 6: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 482
Pulse Width Modulator (PWM) .................................................................................................... 484
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 493
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 494
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 495
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 496
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 497
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 498
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 499
January 09, 201118
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Table of Contents
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 500
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 501
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 502
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 502
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 502
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 504
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 504
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 504
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 507
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 507
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 507
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 508
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 508
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 508
Register 22: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 509
Register 23: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 509
Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 509
Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 510
Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 510
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 510
Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 511
Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 511
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 511
Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 512
Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 512
Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 512
Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 513
Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 513
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 513
Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 516
Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 516
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 516
Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 519
Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 519
Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 519
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 520
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 520
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 520
Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 521
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 521
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 521
19January 09, 2011
Texas Instruments-Production Data
Stellaris® LM3S811 Microcontroller
Revision History
The revision history table notes changes made between the indicated revisions of the LM3S811
data sheet.
Table 1. Revision History
DescriptionRevisionDate
■ In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ
to SYSRESREQ.
■ Added DEBUG (Debug Priority) bit field to System Handler Priority 3 (SYSPRI3) register.
■ Added "Reset Sources" table to System Control chapter.
■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported.
■ Added note that specific module clocks must be enabled before that module's registers can be
programmed. There must be a delay of 3 system clocks after the module clock is enabled before
any of that module's registers are accessed.
■ Changed I
2
C slave register base addresses and offsets to be relative to the I
2
C module base address
of 0x4002.0000 , so register bases and offsets were changed for all I
2
C slave registers. Note that
the hw_i2c.h file in the StellarisWare Driver Library uses a base address of 0x4002.0800 for the I
2
C
slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that
StellarisWare uses the old slave base address for these offsets.
■ Corrected nonlinearity and offset error parameters (E
L
, E
D
and E
O
) in ADC Characteristics table.
■ Added specification for maximum input voltage on a non-power pin when the microcontroller is
unpowered (V
NON
parameter in Maximum Ratings table).
■ Additional minor data sheet clarifications and corrections.
9102January 2011
■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two
new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was
added, including all the Cortex-M3 registers.
■ Changed register names to be consistent with StellarisWare
®
names: the Cortex-M3 Interrupt
Control and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and
the Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0)
register.
■ Added clarification of instruction execution during Flash operations.
■ Modified Figure 7-2 on page 228 to clarify operation of the GPIO inputs when used as an alternate
function.
■ Added caution not to apply a Low value to PB7 when debugging; a Low value on the pin causes
the JTAG controller to be reset, resulting in a loss of JTAG communication.
■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.
■ Added missing table "Connections for Unused Signals" (Table 17-5 on page 530).
■ In Electrical Characteristics chapter:
– Added I
LKG
parameter (GPIO input leakage current) to Table 19-4 on page 534.
– Corrected values for t
CLKRF
parameter (SSIClk rise/fall time) in Table 19-16 on page 542.
■ Added dimensions for Tray and Tape and Reel shipping mediums.
7783September 2010
January 09, 201120
Texas Instruments-Production Data
Revision History
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